diff options
author | Vinod G <vinodg@nvidia.com> | 2018-05-18 19:38:55 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-24 07:38:06 -0400 |
commit | 0f81c5616b04dea9772f490636d0a1959a42774e (patch) | |
tree | 6272bffd42d076d14739843fd50ec12ab582029b /drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c | |
parent | d9128f697c41a61c02fa7511ecb1f8bbf0e081a2 (diff) |
gpu: nvgpu: Code updates for MISRA violations
Regenerated the gating_reglist.c files for various
chips after fixing the script for MISRA C-2012
violations
Rule 15.5: Multiple points of exit detected
Rule 15.6: "if" body without compound statement
Rule 10.3: Implicit conversions of 64bit to 32bit int
Rule 7.2: Const must be declared with "U"
Rule 5.7: Tags with name xxx already declared
Add preprocessor conditional gaurds in
gating_reglist header files
JIRA NVGPU-671
JIRA NVGPU-656
JIRA NVGPU-688
JIRA NVGPU-686
JIRA NVGPU-644
Change-Id: Ie5a688cb8c39f072d2a15d86fb0ee0f2039a2cf1
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1724444
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c')
-rw-r--r-- | drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c | 812 |
1 files changed, 370 insertions, 442 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c index 4355f698..70acd7db 100644 --- a/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c +++ b/drivers/gpu/nvgpu/common/clock_gating/gp10b_gating_reglist.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -22,155 +22,153 @@ | |||
22 | * This file is autogenerated. Do not edit. | 22 | * This file is autogenerated. Do not edit. |
23 | */ | 23 | */ |
24 | 24 | ||
25 | #ifndef __gp10b_gating_reglist_h__ | 25 | #include <nvgpu/types.h> |
26 | #define __gp10b_gating_reglist_h__ | 26 | #include <nvgpu/io.h> |
27 | #include <nvgpu/enabled.h> | ||
27 | 28 | ||
29 | #include "gating_reglist.h" | ||
28 | #include "gp10b_gating_reglist.h" | 30 | #include "gp10b_gating_reglist.h" |
29 | #include <nvgpu/enabled.h> | ||
30 | 31 | ||
31 | struct gating_desc { | 32 | #define GATING_DESC_SIZE (u32)(sizeof(struct gating_desc)) |
32 | u32 addr; | 33 | |
33 | u32 prod; | ||
34 | u32 disable; | ||
35 | }; | ||
36 | /* slcg bus */ | 34 | /* slcg bus */ |
37 | static const struct gating_desc gp10b_slcg_bus[] = { | 35 | static const struct gating_desc gp10b_slcg_bus[] = { |
38 | {.addr = 0x00001c04, .prod = 0x00000000, .disable = 0x000003fe}, | 36 | {.addr = 0x00001c04U, .prod = 0x00000000U, .disable = 0x000003feU}, |
39 | }; | 37 | }; |
40 | 38 | ||
41 | /* slcg ce2 */ | 39 | /* slcg ce2 */ |
42 | static const struct gating_desc gp10b_slcg_ce2[] = { | 40 | static const struct gating_desc gp10b_slcg_ce2[] = { |
43 | {.addr = 0x00104204, .prod = 0x00000000, .disable = 0x000007fe}, | 41 | {.addr = 0x00104204U, .prod = 0x00000040U, .disable = 0x000007feU}, |
44 | }; | 42 | }; |
45 | 43 | ||
46 | /* slcg chiplet */ | 44 | /* slcg chiplet */ |
47 | static const struct gating_desc gp10b_slcg_chiplet[] = { | 45 | static const struct gating_desc gp10b_slcg_chiplet[] = { |
48 | {.addr = 0x0010c07c, .prod = 0x00000000, .disable = 0x00000007}, | 46 | {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
49 | {.addr = 0x0010e07c, .prod = 0x00000000, .disable = 0x00000007}, | 47 | {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
50 | {.addr = 0x0010d07c, .prod = 0x00000000, .disable = 0x00000007}, | 48 | {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
51 | {.addr = 0x0010e17c, .prod = 0x00000000, .disable = 0x00000007}, | 49 | {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, |
52 | }; | 50 | }; |
53 | 51 | ||
54 | /* slcg fb */ | 52 | /* slcg fb */ |
55 | static const struct gating_desc gp10b_slcg_fb[] = { | 53 | static const struct gating_desc gp10b_slcg_fb[] = { |
56 | {.addr = 0x00100d14, .prod = 0x00000000, .disable = 0xfffffffe}, | 54 | {.addr = 0x00100d14U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
57 | {.addr = 0x00100c9c, .prod = 0x00000000, .disable = 0x000001fe}, | 55 | {.addr = 0x00100c9cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
58 | }; | 56 | }; |
59 | 57 | ||
60 | /* slcg fifo */ | 58 | /* slcg fifo */ |
61 | static const struct gating_desc gp10b_slcg_fifo[] = { | 59 | static const struct gating_desc gp10b_slcg_fifo[] = { |
62 | {.addr = 0x000026ac, .prod = 0x00000f40, .disable = 0x0001fffe}, | 60 | {.addr = 0x000026acU, .prod = 0x00000f40U, .disable = 0x0001fffeU}, |
63 | }; | 61 | }; |
64 | 62 | ||
65 | /* slcg gr */ | 63 | /* slcg gr */ |
66 | static const struct gating_desc gp10b_slcg_gr[] = { | 64 | static const struct gating_desc gp10b_slcg_gr[] = { |
67 | {.addr = 0x004041f4, .prod = 0x00000002, .disable = 0x03fffffe}, | 65 | {.addr = 0x004041f4U, .prod = 0x00000002U, .disable = 0x03fffffeU}, |
68 | {.addr = 0x0040917c, .prod = 0x00020008, .disable = 0x0003fffe}, | 66 | {.addr = 0x0040917cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
69 | {.addr = 0x00409894, .prod = 0x00000040, .disable = 0x03fffffe}, | 67 | {.addr = 0x00409894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
70 | {.addr = 0x004078c4, .prod = 0x00000000, .disable = 0x000001fe}, | 68 | {.addr = 0x004078c4U, .prod = 0x00000000U, .disable = 0x000001feU}, |
71 | {.addr = 0x00406004, .prod = 0x00000200, .disable = 0x0001fffe}, | 69 | {.addr = 0x00406004U, .prod = 0x00000200U, .disable = 0x0001fffeU}, |
72 | {.addr = 0x00405864, .prod = 0x00000000, .disable = 0x000001fe}, | 70 | {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, |
73 | {.addr = 0x00405910, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 71 | {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
74 | {.addr = 0x00408044, .prod = 0x00000000, .disable = 0x000007fe}, | 72 | {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, |
75 | {.addr = 0x00407004, .prod = 0x00000000, .disable = 0x000001fe}, | 73 | {.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU}, |
76 | {.addr = 0x0041a17c, .prod = 0x00020008, .disable = 0x0003fffe}, | 74 | {.addr = 0x0041a17cU, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
77 | {.addr = 0x0041a894, .prod = 0x00000040, .disable = 0x03fffffe}, | 75 | {.addr = 0x0041a894U, .prod = 0x00000040U, .disable = 0x03fffffeU}, |
78 | {.addr = 0x00418504, .prod = 0x00000000, .disable = 0x0007fffe}, | 76 | {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, |
79 | {.addr = 0x0041860c, .prod = 0x00000000, .disable = 0x000001fe}, | 77 | {.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
80 | {.addr = 0x0041868c, .prod = 0x00000000, .disable = 0x0000001e}, | 78 | {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, |
81 | {.addr = 0x0041871c, .prod = 0x00000000, .disable = 0x0000003e}, | 79 | {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
82 | {.addr = 0x00418388, .prod = 0x00000000, .disable = 0x00000001}, | 80 | {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, |
83 | {.addr = 0x0041882c, .prod = 0x00000000, .disable = 0x0001fffe}, | 81 | {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
84 | {.addr = 0x00418bc0, .prod = 0x00000000, .disable = 0x000001fe}, | 82 | {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, |
85 | {.addr = 0x00418974, .prod = 0x00000000, .disable = 0x0001fffe}, | 83 | {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
86 | {.addr = 0x00418c74, .prod = 0xffffffc0, .disable = 0xfffffffe}, | 84 | {.addr = 0x00418c74U, .prod = 0xffffffc0U, .disable = 0xfffffffeU}, |
87 | {.addr = 0x00418cf4, .prod = 0xfffffffc, .disable = 0xfffffffe}, | 85 | {.addr = 0x00418cf4U, .prod = 0xfffffffcU, .disable = 0xfffffffeU}, |
88 | {.addr = 0x00418d74, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 86 | {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
89 | {.addr = 0x00418f10, .prod = 0xffffffe0, .disable = 0xfffffffe}, | 87 | {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, |
90 | {.addr = 0x00418e10, .prod = 0xfffffffe, .disable = 0xfffffffe}, | 88 | {.addr = 0x00418e10U, .prod = 0xfffffffeU, .disable = 0xfffffffeU}, |
91 | {.addr = 0x00419024, .prod = 0x000001fe, .disable = 0x000001fe}, | 89 | {.addr = 0x00419024U, .prod = 0x000001feU, .disable = 0x000001feU}, |
92 | {.addr = 0x0041889c, .prod = 0x00000000, .disable = 0x000001fe}, | 90 | {.addr = 0x0041889cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
93 | {.addr = 0x00419d24, .prod = 0x00000000, .disable = 0x0000ffff}, | 91 | {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
94 | {.addr = 0x00419a44, .prod = 0x00000000, .disable = 0x0000000e}, | 92 | {.addr = 0x00419a44U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
95 | {.addr = 0x00419a4c, .prod = 0x00000000, .disable = 0x000001fe}, | 93 | {.addr = 0x00419a4cU, .prod = 0x00000000U, .disable = 0x000001feU}, |
96 | {.addr = 0x00419a54, .prod = 0x00000000, .disable = 0x0000003e}, | 94 | {.addr = 0x00419a54U, .prod = 0x00000000U, .disable = 0x0000003eU}, |
97 | {.addr = 0x00419a5c, .prod = 0x00000000, .disable = 0x0000000e}, | 95 | {.addr = 0x00419a5cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
98 | {.addr = 0x00419a64, .prod = 0x00000000, .disable = 0x000001fe}, | 96 | {.addr = 0x00419a64U, .prod = 0x00000000U, .disable = 0x000001feU}, |
99 | {.addr = 0x00419a6c, .prod = 0x00000000, .disable = 0x0000000e}, | 97 | {.addr = 0x00419a6cU, .prod = 0x00000000U, .disable = 0x0000000eU}, |
100 | {.addr = 0x00419a74, .prod = 0x00000000, .disable = 0x0000000e}, | 98 | {.addr = 0x00419a74U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
101 | {.addr = 0x00419a7c, .prod = 0x00000000, .disable = 0x0000003e}, | 99 | {.addr = 0x00419a7cU, .prod = 0x00000000U, .disable = 0x0000003eU}, |
102 | {.addr = 0x00419a84, .prod = 0x00000000, .disable = 0x0000000e}, | 100 | {.addr = 0x00419a84U, .prod = 0x00000000U, .disable = 0x0000000eU}, |
103 | {.addr = 0x0041986c, .prod = 0x00000104, .disable = 0x00fffffe}, | 101 | {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, |
104 | {.addr = 0x00419cd8, .prod = 0x00000000, .disable = 0x001ffffe}, | 102 | {.addr = 0x00419cd8U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
105 | {.addr = 0x00419ce0, .prod = 0x00000000, .disable = 0x001ffffe}, | 103 | {.addr = 0x00419ce0U, .prod = 0x00000000U, .disable = 0x001ffffeU}, |
106 | {.addr = 0x00419c74, .prod = 0x0000001e, .disable = 0x0000001e}, | 104 | {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, |
107 | {.addr = 0x00419fd4, .prod = 0x00000000, .disable = 0x0003fffe}, | 105 | {.addr = 0x00419fd4U, .prod = 0x00000000U, .disable = 0x0003fffeU}, |
108 | {.addr = 0x00419fdc, .prod = 0xffedff00, .disable = 0xfffffffe}, | 106 | {.addr = 0x00419fdcU, .prod = 0xffedff00U, .disable = 0xfffffffeU}, |
109 | {.addr = 0x00419fe4, .prod = 0x00001b00, .disable = 0x00001ffe}, | 107 | {.addr = 0x00419fe4U, .prod = 0x00001b00U, .disable = 0x00001ffeU}, |
110 | {.addr = 0x00419ff4, .prod = 0x00000000, .disable = 0x00003ffe}, | 108 | {.addr = 0x00419ff4U, .prod = 0x00000000U, .disable = 0x00003ffeU}, |
111 | {.addr = 0x00419ffc, .prod = 0x00000000, .disable = 0x0001fffe}, | 109 | {.addr = 0x00419ffcU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
112 | {.addr = 0x0041be2c, .prod = 0x04115fc0, .disable = 0xfffffffe}, | 110 | {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, |
113 | {.addr = 0x0041bfec, .prod = 0xfffffff0, .disable = 0xfffffffe}, | 111 | {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, |
114 | {.addr = 0x0041bed4, .prod = 0xfffffff8, .disable = 0xfffffffe}, | 112 | {.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, |
115 | {.addr = 0x00408814, .prod = 0x00000000, .disable = 0x0001fffe}, | 113 | {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
116 | {.addr = 0x00408a84, .prod = 0x00000000, .disable = 0x0001fffe}, | 114 | {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
117 | {.addr = 0x004089ac, .prod = 0x00000000, .disable = 0x0001fffe}, | 115 | {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, |
118 | {.addr = 0x00408a24, .prod = 0x00000000, .disable = 0x0000ffff}, | 116 | {.addr = 0x00408a24U, .prod = 0x00000000U, .disable = 0x0000ffffU}, |
119 | }; | 117 | }; |
120 | 118 | ||
121 | /* slcg ltc */ | 119 | /* slcg ltc */ |
122 | static const struct gating_desc gp10b_slcg_ltc[] = { | 120 | static const struct gating_desc gp10b_slcg_ltc[] = { |
123 | {.addr = 0x0017e050, .prod = 0x00000000, .disable = 0xfffffffe}, | 121 | {.addr = 0x0017e050U, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
124 | {.addr = 0x0017e35c, .prod = 0x00000000, .disable = 0xfffffffe}, | 122 | {.addr = 0x0017e35cU, .prod = 0x00000000U, .disable = 0xfffffffeU}, |
125 | }; | 123 | }; |
126 | 124 | ||
127 | /* slcg perf */ | 125 | /* slcg perf */ |
128 | static const struct gating_desc gp10b_slcg_perf[] = { | 126 | static const struct gating_desc gp10b_slcg_perf[] = { |
129 | {.addr = 0x001be018, .prod = 0x000001ff, .disable = 0x00000000}, | 127 | {.addr = 0x001be018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
130 | {.addr = 0x001bc018, .prod = 0x000001ff, .disable = 0x00000000}, | 128 | {.addr = 0x001bc018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
131 | {.addr = 0x001b8018, .prod = 0x000001ff, .disable = 0x00000000}, | 129 | {.addr = 0x001b8018U, .prod = 0x000001ffU, .disable = 0x00000000U}, |
132 | {.addr = 0x001b4124, .prod = 0x00000001, .disable = 0x00000000}, | 130 | {.addr = 0x001b4124U, .prod = 0x00000001U, .disable = 0x00000000U}, |
133 | }; | 131 | }; |
134 | 132 | ||
135 | /* slcg PriRing */ | 133 | /* slcg PriRing */ |
136 | static const struct gating_desc gp10b_slcg_priring[] = { | 134 | static const struct gating_desc gp10b_slcg_priring[] = { |
137 | {.addr = 0x001200a8, .prod = 0x00000000, .disable = 0x00000001}, | 135 | {.addr = 0x001200a8U, .prod = 0x00000000U, .disable = 0x00000001U}, |
138 | }; | 136 | }; |
139 | 137 | ||
140 | /* slcg pwr_csb */ | 138 | /* slcg pwr_csb */ |
141 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { | 139 | static const struct gating_desc gp10b_slcg_pwr_csb[] = { |
142 | {.addr = 0x00000134, .prod = 0x00020008, .disable = 0x0003fffe}, | 140 | {.addr = 0x00000134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
143 | {.addr = 0x00000e74, .prod = 0x00000000, .disable = 0x0000000f}, | 141 | {.addr = 0x00000e74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
144 | {.addr = 0x00000a74, .prod = 0x00004000, .disable = 0x00007ffe}, | 142 | {.addr = 0x00000a74U, .prod = 0x00004000U, .disable = 0x00007ffeU}, |
145 | {.addr = 0x000016b8, .prod = 0x00000000, .disable = 0x0000000f}, | 143 | {.addr = 0x000016b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
146 | }; | 144 | }; |
147 | 145 | ||
148 | /* slcg pmu */ | 146 | /* slcg pmu */ |
149 | static const struct gating_desc gp10b_slcg_pmu[] = { | 147 | static const struct gating_desc gp10b_slcg_pmu[] = { |
150 | {.addr = 0x0010a134, .prod = 0x00020008, .disable = 0x0003fffe}, | 148 | {.addr = 0x0010a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, |
151 | {.addr = 0x0010aa74, .prod = 0x00004000, .disable = 0x00007ffe}, | 149 | {.addr = 0x0010aa74U, .prod = 0x00004000U, .disable = 0x00007ffeU}, |
152 | {.addr = 0x0010ae74, .prod = 0x00000000, .disable = 0x0000000f}, | 150 | {.addr = 0x0010ae74U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
153 | }; | 151 | }; |
154 | 152 | ||
155 | /* therm gr */ | 153 | /* therm gr */ |
156 | static const struct gating_desc gp10b_slcg_therm[] = { | 154 | static const struct gating_desc gp10b_slcg_therm[] = { |
157 | {.addr = 0x000206b8, .prod = 0x00000000, .disable = 0x0000000f}, | 155 | {.addr = 0x000206b8U, .prod = 0x00000000U, .disable = 0x0000000fU}, |
158 | }; | 156 | }; |
159 | 157 | ||
160 | /* slcg Xbar */ | 158 | /* slcg Xbar */ |
161 | static const struct gating_desc gp10b_slcg_xbar[] = { | 159 | static const struct gating_desc gp10b_slcg_xbar[] = { |
162 | {.addr = 0x0013cbe4, .prod = 0x00000000, .disable = 0x1ffffffe}, | 160 | {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
163 | {.addr = 0x0013cc04, .prod = 0x00000000, .disable = 0x1ffffffe}, | 161 | {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, |
164 | }; | 162 | }; |
165 | 163 | ||
166 | /* blcg bus */ | 164 | /* blcg bus */ |
167 | static const struct gating_desc gp10b_blcg_bus[] = { | 165 | static const struct gating_desc gp10b_blcg_bus[] = { |
168 | {.addr = 0x00001c00, .prod = 0x00000042, .disable = 0x00000000}, | 166 | {.addr = 0x00001c00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
169 | }; | 167 | }; |
170 | 168 | ||
171 | /* blcg ce */ | 169 | /* blcg ce */ |
172 | static const struct gating_desc gp10b_blcg_ce[] = { | 170 | static const struct gating_desc gp10b_blcg_ce[] = { |
173 | {.addr = 0x00104200, .prod = 0x00008242, .disable = 0x00000000}, | 171 | {.addr = 0x00104200U, .prod = 0x00008242U, .disable = 0x00000000U}, |
174 | }; | 172 | }; |
175 | 173 | ||
176 | /* blcg ctxsw prog */ | 174 | /* blcg ctxsw prog */ |
@@ -179,98 +177,100 @@ static const struct gating_desc gp10b_blcg_ctxsw_prog[] = { | |||
179 | 177 | ||
180 | /* blcg fb */ | 178 | /* blcg fb */ |
181 | static const struct gating_desc gp10b_blcg_fb[] = { | 179 | static const struct gating_desc gp10b_blcg_fb[] = { |
182 | {.addr = 0x00100d10, .prod = 0x0000c242, .disable = 0x00000000}, | 180 | {.addr = 0x00100d10U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
183 | {.addr = 0x00100d30, .prod = 0x0000c242, .disable = 0x00000000}, | 181 | {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
184 | {.addr = 0x00100d3c, .prod = 0x00000242, .disable = 0x00000000}, | 182 | {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, |
185 | {.addr = 0x00100d48, .prod = 0x0000c242, .disable = 0x00000000}, | 183 | {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
186 | {.addr = 0x00100c98, .prod = 0x00004242, .disable = 0x00000000}, | 184 | /* fix priv error */ |
185 | /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/ | ||
186 | {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, | ||
187 | }; | 187 | }; |
188 | 188 | ||
189 | /* blcg fifo */ | 189 | /* blcg fifo */ |
190 | static const struct gating_desc gp10b_blcg_fifo[] = { | 190 | static const struct gating_desc gp10b_blcg_fifo[] = { |
191 | {.addr = 0x000026a4, .prod = 0x0000c242, .disable = 0x00000000}, | 191 | {.addr = 0x000026a4U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
192 | }; | 192 | }; |
193 | 193 | ||
194 | /* blcg gr */ | 194 | /* blcg gr */ |
195 | static const struct gating_desc gp10b_blcg_gr[] = { | 195 | static const struct gating_desc gp10b_blcg_gr[] = { |
196 | {.addr = 0x004041f0, .prod = 0x0000c646, .disable = 0x00000000}, | 196 | {.addr = 0x004041f0U, .prod = 0x0000c646U, .disable = 0x00000000U}, |
197 | {.addr = 0x00409890, .prod = 0x0000007f, .disable = 0x00000000}, | 197 | {.addr = 0x00409890U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
198 | {.addr = 0x004098b0, .prod = 0x0000007f, .disable = 0x00000000}, | 198 | {.addr = 0x004098b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
199 | {.addr = 0x004078c0, .prod = 0x00004242, .disable = 0x00000000}, | 199 | {.addr = 0x004078c0U, .prod = 0x00004242U, .disable = 0x00000000U}, |
200 | {.addr = 0x00406000, .prod = 0x0000c444, .disable = 0x00000000}, | 200 | {.addr = 0x00406000U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
201 | {.addr = 0x00405860, .prod = 0x0000c242, .disable = 0x00000000}, | 201 | {.addr = 0x00405860U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
202 | {.addr = 0x0040590c, .prod = 0x0000c444, .disable = 0x00000000}, | 202 | {.addr = 0x0040590cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
203 | {.addr = 0x00408040, .prod = 0x0000c444, .disable = 0x00000000}, | 203 | {.addr = 0x00408040U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
204 | {.addr = 0x00407000, .prod = 0x4000c242, .disable = 0x00000000}, | 204 | {.addr = 0x00407000U, .prod = 0x4000c242U, .disable = 0x00000000U}, |
205 | /* fix priv error */ | 205 | /* fix priv error */ |
206 | /*{.addr = 0x00405bf0, .prod = 0x0000c444, .disable = 0x00000000},*/ | 206 | /*{.addr = 0x00405bf0U, .prod = 0x0000c444U, .disable = 0x00000000U},*/ |
207 | {.addr = 0x0041a890, .prod = 0x0000427f, .disable = 0x00000000}, | 207 | {.addr = 0x0041a890U, .prod = 0x0000427fU, .disable = 0x00000000U}, |
208 | {.addr = 0x0041a8b0, .prod = 0x0000007f, .disable = 0x00000000}, | 208 | {.addr = 0x0041a8b0U, .prod = 0x0000007fU, .disable = 0x00000000U}, |
209 | {.addr = 0x00418500, .prod = 0x0000c244, .disable = 0x00000000}, | 209 | {.addr = 0x00418500U, .prod = 0x0000c244U, .disable = 0x00000000U}, |
210 | {.addr = 0x00418608, .prod = 0x0000c242, .disable = 0x00000000}, | 210 | {.addr = 0x00418608U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
211 | {.addr = 0x00418688, .prod = 0x0000c242, .disable = 0x00000000}, | 211 | {.addr = 0x00418688U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
212 | {.addr = 0x00418718, .prod = 0x00000042, .disable = 0x00000000}, | 212 | {.addr = 0x00418718U, .prod = 0x00000042U, .disable = 0x00000000U}, |
213 | {.addr = 0x00418828, .prod = 0x00008444, .disable = 0x00000000}, | 213 | {.addr = 0x00418828U, .prod = 0x00008444U, .disable = 0x00000000U}, |
214 | {.addr = 0x00418bbc, .prod = 0x0000c242, .disable = 0x00000000}, | 214 | {.addr = 0x00418bbcU, .prod = 0x0000c242U, .disable = 0x00000000U}, |
215 | {.addr = 0x00418970, .prod = 0x0000c242, .disable = 0x00000000}, | 215 | {.addr = 0x00418970U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
216 | {.addr = 0x00418c70, .prod = 0x0000c444, .disable = 0x00000000}, | 216 | {.addr = 0x00418c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
217 | {.addr = 0x00418cf0, .prod = 0x0000c444, .disable = 0x00000000}, | 217 | {.addr = 0x00418cf0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
218 | {.addr = 0x00418d70, .prod = 0x0000c444, .disable = 0x00000000}, | 218 | {.addr = 0x00418d70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
219 | {.addr = 0x00418f0c, .prod = 0x0000c444, .disable = 0x00000000}, | 219 | {.addr = 0x00418f0cU, .prod = 0x0000c444U, .disable = 0x00000000U}, |
220 | {.addr = 0x00418e0c, .prod = 0x00008444, .disable = 0x00000000}, | 220 | {.addr = 0x00418e0cU, .prod = 0x00008444U, .disable = 0x00000000U}, |
221 | {.addr = 0x00419020, .prod = 0x0000c242, .disable = 0x00000000}, | 221 | {.addr = 0x00419020U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
222 | {.addr = 0x00419038, .prod = 0x00000042, .disable = 0x00000000}, | 222 | {.addr = 0x00419038U, .prod = 0x00000042U, .disable = 0x00000000U}, |
223 | {.addr = 0x00418898, .prod = 0x00004242, .disable = 0x00000000}, | 223 | {.addr = 0x00418898U, .prod = 0x00004242U, .disable = 0x00000000U}, |
224 | {.addr = 0x00419a40, .prod = 0x0000c242, .disable = 0x00000000}, | 224 | {.addr = 0x00419a40U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
225 | {.addr = 0x00419a48, .prod = 0x0000c242, .disable = 0x00000000}, | 225 | {.addr = 0x00419a48U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
226 | {.addr = 0x00419a50, .prod = 0x0000c242, .disable = 0x00000000}, | 226 | {.addr = 0x00419a50U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
227 | {.addr = 0x00419a58, .prod = 0x0000c242, .disable = 0x00000000}, | 227 | {.addr = 0x00419a58U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
228 | {.addr = 0x00419a60, .prod = 0x0000c242, .disable = 0x00000000}, | 228 | {.addr = 0x00419a60U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
229 | {.addr = 0x00419a68, .prod = 0x0000c242, .disable = 0x00000000}, | 229 | {.addr = 0x00419a68U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
230 | {.addr = 0x00419a70, .prod = 0x0000c242, .disable = 0x00000000}, | 230 | {.addr = 0x00419a70U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
231 | {.addr = 0x00419a78, .prod = 0x0000c242, .disable = 0x00000000}, | 231 | {.addr = 0x00419a78U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
232 | {.addr = 0x00419a80, .prod = 0x0000c242, .disable = 0x00000000}, | 232 | {.addr = 0x00419a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
233 | {.addr = 0x00419868, .prod = 0x00008242, .disable = 0x00000000}, | 233 | {.addr = 0x00419868U, .prod = 0x00008242U, .disable = 0x00000000U}, |
234 | {.addr = 0x00419cd4, .prod = 0x00000002, .disable = 0x00000000}, | 234 | {.addr = 0x00419cd4U, .prod = 0x00000002U, .disable = 0x00000000U}, |
235 | {.addr = 0x00419cdc, .prod = 0x00000002, .disable = 0x00000000}, | 235 | {.addr = 0x00419cdcU, .prod = 0x00000002U, .disable = 0x00000000U}, |
236 | {.addr = 0x00419c70, .prod = 0x0000c444, .disable = 0x00000000}, | 236 | {.addr = 0x00419c70U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
237 | {.addr = 0x00419fd0, .prod = 0x0000c044, .disable = 0x00000000}, | 237 | {.addr = 0x00419fd0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
238 | {.addr = 0x00419fd8, .prod = 0x0000c046, .disable = 0x00000000}, | 238 | {.addr = 0x00419fd8U, .prod = 0x0000c046U, .disable = 0x00000000U}, |
239 | {.addr = 0x00419fe0, .prod = 0x0000c044, .disable = 0x00000000}, | 239 | {.addr = 0x00419fe0U, .prod = 0x0000c044U, .disable = 0x00000000U}, |
240 | {.addr = 0x00419fe8, .prod = 0x0000c042, .disable = 0x00000000}, | 240 | {.addr = 0x00419fe8U, .prod = 0x0000c042U, .disable = 0x00000000U}, |
241 | {.addr = 0x00419ff0, .prod = 0x0000c045, .disable = 0x00000000}, | 241 | {.addr = 0x00419ff0U, .prod = 0x0000c045U, .disable = 0x00000000U}, |
242 | {.addr = 0x00419ff8, .prod = 0x00000002, .disable = 0x00000000}, | 242 | {.addr = 0x00419ff8U, .prod = 0x00000002U, .disable = 0x00000000U}, |
243 | {.addr = 0x00419f90, .prod = 0x00000002, .disable = 0x00000000}, | 243 | {.addr = 0x00419f90U, .prod = 0x00000002U, .disable = 0x00000000U}, |
244 | {.addr = 0x0041be28, .prod = 0x00008242, .disable = 0x00000000}, | 244 | {.addr = 0x0041be28U, .prod = 0x00008242U, .disable = 0x00000000U}, |
245 | {.addr = 0x0041bfe8, .prod = 0x0000c444, .disable = 0x00000000}, | 245 | {.addr = 0x0041bfe8U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
246 | {.addr = 0x0041bed0, .prod = 0x0000c444, .disable = 0x00000000}, | 246 | {.addr = 0x0041bed0U, .prod = 0x0000c444U, .disable = 0x00000000U}, |
247 | {.addr = 0x00408810, .prod = 0x0000c242, .disable = 0x00000000}, | 247 | {.addr = 0x00408810U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
248 | {.addr = 0x00408a80, .prod = 0x0000c242, .disable = 0x00000000}, | 248 | {.addr = 0x00408a80U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
249 | {.addr = 0x004089a8, .prod = 0x0000c242, .disable = 0x00000000}, | 249 | {.addr = 0x004089a8U, .prod = 0x0000c242U, .disable = 0x00000000U}, |
250 | }; | 250 | }; |
251 | 251 | ||
252 | /* blcg ltc */ | 252 | /* blcg ltc */ |
253 | static const struct gating_desc gp10b_blcg_ltc[] = { | 253 | static const struct gating_desc gp10b_blcg_ltc[] = { |
254 | {.addr = 0x0017e030, .prod = 0x00000044, .disable = 0x00000000}, | 254 | {.addr = 0x0017e030U, .prod = 0x00000044U, .disable = 0x00000000U}, |
255 | {.addr = 0x0017e040, .prod = 0x00000044, .disable = 0x00000000}, | 255 | {.addr = 0x0017e040U, .prod = 0x00000044U, .disable = 0x00000000U}, |
256 | {.addr = 0x0017e3e0, .prod = 0x00000044, .disable = 0x00000000}, | 256 | {.addr = 0x0017e3e0U, .prod = 0x00000044U, .disable = 0x00000000U}, |
257 | {.addr = 0x0017e3c8, .prod = 0x00000044, .disable = 0x00000000}, | 257 | {.addr = 0x0017e3c8U, .prod = 0x00000044U, .disable = 0x00000000U}, |
258 | }; | 258 | }; |
259 | 259 | ||
260 | /* blcg pwr_csb */ | 260 | /* blcg pwr_csb */ |
261 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { | 261 | static const struct gating_desc gp10b_blcg_pwr_csb[] = { |
262 | {.addr = 0x00000a70, .prod = 0x00000045, .disable = 0x00000000}, | 262 | {.addr = 0x00000a70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
263 | }; | 263 | }; |
264 | 264 | ||
265 | /* blcg pmu */ | 265 | /* blcg pmu */ |
266 | static const struct gating_desc gp10b_blcg_pmu[] = { | 266 | static const struct gating_desc gp10b_blcg_pmu[] = { |
267 | {.addr = 0x0010aa70, .prod = 0x00000045, .disable = 0x00000000}, | 267 | {.addr = 0x0010aa70U, .prod = 0x00000045U, .disable = 0x00000000U}, |
268 | }; | 268 | }; |
269 | 269 | ||
270 | /* blcg Xbar */ | 270 | /* blcg Xbar */ |
271 | static const struct gating_desc gp10b_blcg_xbar[] = { | 271 | static const struct gating_desc gp10b_blcg_xbar[] = { |
272 | {.addr = 0x0013cbe0, .prod = 0x00000042, .disable = 0x00000000}, | 272 | {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, |
273 | {.addr = 0x0013cc00, .prod = 0x00000042, .disable = 0x00000000}, | 273 | {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, |
274 | }; | 274 | }; |
275 | 275 | ||
276 | /* pg gr */ | 276 | /* pg gr */ |
@@ -282,18 +282,15 @@ void gp10b_slcg_bus_load_gating_prod(struct gk20a *g, | |||
282 | bool prod) | 282 | bool prod) |
283 | { | 283 | { |
284 | u32 i; | 284 | u32 i; |
285 | u32 size = sizeof(gp10b_slcg_bus) / sizeof(struct gating_desc); | 285 | u32 size = (u32)(sizeof(gp10b_slcg_bus) / GATING_DESC_SIZE); |
286 | 286 | ||
287 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 287 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
288 | return; | 288 | for (i = 0; i < size; i++) { |
289 | 289 | u32 reg = gp10b_slcg_bus[i].addr; | |
290 | for (i = 0; i < size; i++) { | 290 | u32 val = prod ? gp10b_slcg_bus[i].prod : |
291 | if (prod) | 291 | gp10b_slcg_bus[i].disable; |
292 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | 292 | gk20a_writel(g, reg, val); |
293 | gp10b_slcg_bus[i].prod); | 293 | } |
294 | else | ||
295 | gk20a_writel(g, gp10b_slcg_bus[i].addr, | ||
296 | gp10b_slcg_bus[i].disable); | ||
297 | } | 294 | } |
298 | } | 295 | } |
299 | 296 | ||
@@ -301,18 +298,15 @@ void gp10b_slcg_ce2_load_gating_prod(struct gk20a *g, | |||
301 | bool prod) | 298 | bool prod) |
302 | { | 299 | { |
303 | u32 i; | 300 | u32 i; |
304 | u32 size = sizeof(gp10b_slcg_ce2) / sizeof(struct gating_desc); | 301 | u32 size = (u32)(sizeof(gp10b_slcg_ce2) / GATING_DESC_SIZE); |
305 | 302 | ||
306 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 303 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
307 | return; | 304 | for (i = 0; i < size; i++) { |
308 | 305 | u32 reg = gp10b_slcg_ce2[i].addr; | |
309 | for (i = 0; i < size; i++) { | 306 | u32 val = prod ? gp10b_slcg_ce2[i].prod : |
310 | if (prod) | 307 | gp10b_slcg_ce2[i].disable; |
311 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | 308 | gk20a_writel(g, reg, val); |
312 | gp10b_slcg_ce2[i].prod); | 309 | } |
313 | else | ||
314 | gk20a_writel(g, gp10b_slcg_ce2[i].addr, | ||
315 | gp10b_slcg_ce2[i].disable); | ||
316 | } | 310 | } |
317 | } | 311 | } |
318 | 312 | ||
@@ -320,42 +314,38 @@ void gp10b_slcg_chiplet_load_gating_prod(struct gk20a *g, | |||
320 | bool prod) | 314 | bool prod) |
321 | { | 315 | { |
322 | u32 i; | 316 | u32 i; |
323 | u32 size = sizeof(gp10b_slcg_chiplet) / sizeof(struct gating_desc); | 317 | u32 size = (u32)(sizeof(gp10b_slcg_chiplet) / GATING_DESC_SIZE); |
324 | 318 | ||
325 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 319 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
326 | return; | 320 | for (i = 0; i < size; i++) { |
327 | 321 | u32 reg = gp10b_slcg_chiplet[i].addr; | |
328 | for (i = 0; i < size; i++) { | 322 | u32 val = prod ? gp10b_slcg_chiplet[i].prod : |
329 | if (prod) | 323 | gp10b_slcg_chiplet[i].disable; |
330 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | 324 | gk20a_writel(g, reg, val); |
331 | gp10b_slcg_chiplet[i].prod); | 325 | } |
332 | else | ||
333 | gk20a_writel(g, gp10b_slcg_chiplet[i].addr, | ||
334 | gp10b_slcg_chiplet[i].disable); | ||
335 | } | 326 | } |
336 | } | 327 | } |
337 | 328 | ||
338 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | 329 | void gp10b_slcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, |
339 | bool prod) | 330 | bool prod) |
340 | { | 331 | { |
332 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
333 | } | ||
341 | } | 334 | } |
342 | 335 | ||
343 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, | 336 | void gp10b_slcg_fb_load_gating_prod(struct gk20a *g, |
344 | bool prod) | 337 | bool prod) |
345 | { | 338 | { |
346 | u32 i; | 339 | u32 i; |
347 | u32 size = sizeof(gp10b_slcg_fb) / sizeof(struct gating_desc); | 340 | u32 size = (u32)(sizeof(gp10b_slcg_fb) / GATING_DESC_SIZE); |
348 | 341 | ||
349 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 342 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
350 | return; | 343 | for (i = 0; i < size; i++) { |
351 | 344 | u32 reg = gp10b_slcg_fb[i].addr; | |
352 | for (i = 0; i < size; i++) { | 345 | u32 val = prod ? gp10b_slcg_fb[i].prod : |
353 | if (prod) | 346 | gp10b_slcg_fb[i].disable; |
354 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | 347 | gk20a_writel(g, reg, val); |
355 | gp10b_slcg_fb[i].prod); | 348 | } |
356 | else | ||
357 | gk20a_writel(g, gp10b_slcg_fb[i].addr, | ||
358 | gp10b_slcg_fb[i].disable); | ||
359 | } | 349 | } |
360 | } | 350 | } |
361 | 351 | ||
@@ -363,18 +353,15 @@ void gp10b_slcg_fifo_load_gating_prod(struct gk20a *g, | |||
363 | bool prod) | 353 | bool prod) |
364 | { | 354 | { |
365 | u32 i; | 355 | u32 i; |
366 | u32 size = sizeof(gp10b_slcg_fifo) / sizeof(struct gating_desc); | 356 | u32 size = (u32)(sizeof(gp10b_slcg_fifo) / GATING_DESC_SIZE); |
367 | 357 | ||
368 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 358 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
369 | return; | 359 | for (i = 0; i < size; i++) { |
370 | 360 | u32 reg = gp10b_slcg_fifo[i].addr; | |
371 | for (i = 0; i < size; i++) { | 361 | u32 val = prod ? gp10b_slcg_fifo[i].prod : |
372 | if (prod) | 362 | gp10b_slcg_fifo[i].disable; |
373 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | 363 | gk20a_writel(g, reg, val); |
374 | gp10b_slcg_fifo[i].prod); | 364 | } |
375 | else | ||
376 | gk20a_writel(g, gp10b_slcg_fifo[i].addr, | ||
377 | gp10b_slcg_fifo[i].disable); | ||
378 | } | 365 | } |
379 | } | 366 | } |
380 | 367 | ||
@@ -382,18 +369,15 @@ void gr_gp10b_slcg_gr_load_gating_prod(struct gk20a *g, | |||
382 | bool prod) | 369 | bool prod) |
383 | { | 370 | { |
384 | u32 i; | 371 | u32 i; |
385 | u32 size = sizeof(gp10b_slcg_gr) / sizeof(struct gating_desc); | 372 | u32 size = (u32)(sizeof(gp10b_slcg_gr) / GATING_DESC_SIZE); |
386 | 373 | ||
387 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 374 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
388 | return; | 375 | for (i = 0; i < size; i++) { |
389 | 376 | u32 reg = gp10b_slcg_gr[i].addr; | |
390 | for (i = 0; i < size; i++) { | 377 | u32 val = prod ? gp10b_slcg_gr[i].prod : |
391 | if (prod) | 378 | gp10b_slcg_gr[i].disable; |
392 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | 379 | gk20a_writel(g, reg, val); |
393 | gp10b_slcg_gr[i].prod); | 380 | } |
394 | else | ||
395 | gk20a_writel(g, gp10b_slcg_gr[i].addr, | ||
396 | gp10b_slcg_gr[i].disable); | ||
397 | } | 381 | } |
398 | } | 382 | } |
399 | 383 | ||
@@ -401,18 +385,15 @@ void ltc_gp10b_slcg_ltc_load_gating_prod(struct gk20a *g, | |||
401 | bool prod) | 385 | bool prod) |
402 | { | 386 | { |
403 | u32 i; | 387 | u32 i; |
404 | u32 size = sizeof(gp10b_slcg_ltc) / sizeof(struct gating_desc); | 388 | u32 size = (u32)(sizeof(gp10b_slcg_ltc) / GATING_DESC_SIZE); |
405 | |||
406 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | ||
407 | return; | ||
408 | 389 | ||
390 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { | ||
409 | for (i = 0; i < size; i++) { | 391 | for (i = 0; i < size; i++) { |
410 | if (prod) | 392 | u32 reg = gp10b_slcg_ltc[i].addr; |
411 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | 393 | u32 val = prod ? gp10b_slcg_ltc[i].prod : |
412 | gp10b_slcg_ltc[i].prod); | 394 | gp10b_slcg_ltc[i].disable; |
413 | else | 395 | gk20a_writel(g, reg, val); |
414 | gk20a_writel(g, gp10b_slcg_ltc[i].addr, | 396 | } |
415 | gp10b_slcg_ltc[i].disable); | ||
416 | } | 397 | } |
417 | } | 398 | } |
418 | 399 | ||
@@ -420,18 +401,15 @@ void gp10b_slcg_perf_load_gating_prod(struct gk20a *g, | |||
420 | bool prod) | 401 | bool prod) |
421 | { | 402 | { |
422 | u32 i; | 403 | u32 i; |
423 | u32 size = sizeof(gp10b_slcg_perf) / sizeof(struct gating_desc); | 404 | u32 size = (u32)(sizeof(gp10b_slcg_perf) / GATING_DESC_SIZE); |
424 | 405 | ||
425 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 406 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
426 | return; | 407 | for (i = 0; i < size; i++) { |
427 | 408 | u32 reg = gp10b_slcg_perf[i].addr; | |
428 | for (i = 0; i < size; i++) { | 409 | u32 val = prod ? gp10b_slcg_perf[i].prod : |
429 | if (prod) | 410 | gp10b_slcg_perf[i].disable; |
430 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | 411 | gk20a_writel(g, reg, val); |
431 | gp10b_slcg_perf[i].prod); | 412 | } |
432 | else | ||
433 | gk20a_writel(g, gp10b_slcg_perf[i].addr, | ||
434 | gp10b_slcg_perf[i].disable); | ||
435 | } | 413 | } |
436 | } | 414 | } |
437 | 415 | ||
@@ -439,18 +417,15 @@ void gp10b_slcg_priring_load_gating_prod(struct gk20a *g, | |||
439 | bool prod) | 417 | bool prod) |
440 | { | 418 | { |
441 | u32 i; | 419 | u32 i; |
442 | u32 size = sizeof(gp10b_slcg_priring) / sizeof(struct gating_desc); | 420 | u32 size = (u32)(sizeof(gp10b_slcg_priring) / GATING_DESC_SIZE); |
443 | 421 | ||
444 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 422 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
445 | return; | 423 | for (i = 0; i < size; i++) { |
446 | 424 | u32 reg = gp10b_slcg_priring[i].addr; | |
447 | for (i = 0; i < size; i++) { | 425 | u32 val = prod ? gp10b_slcg_priring[i].prod : |
448 | if (prod) | 426 | gp10b_slcg_priring[i].disable; |
449 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | 427 | gk20a_writel(g, reg, val); |
450 | gp10b_slcg_priring[i].prod); | 428 | } |
451 | else | ||
452 | gk20a_writel(g, gp10b_slcg_priring[i].addr, | ||
453 | gp10b_slcg_priring[i].disable); | ||
454 | } | 429 | } |
455 | } | 430 | } |
456 | 431 | ||
@@ -458,18 +433,15 @@ void gp10b_slcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
458 | bool prod) | 433 | bool prod) |
459 | { | 434 | { |
460 | u32 i; | 435 | u32 i; |
461 | u32 size = sizeof(gp10b_slcg_pwr_csb) / sizeof(struct gating_desc); | 436 | u32 size = (u32)(sizeof(gp10b_slcg_pwr_csb) / GATING_DESC_SIZE); |
462 | 437 | ||
463 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 438 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
464 | return; | 439 | for (i = 0; i < size; i++) { |
465 | 440 | u32 reg = gp10b_slcg_pwr_csb[i].addr; | |
466 | for (i = 0; i < size; i++) { | 441 | u32 val = prod ? gp10b_slcg_pwr_csb[i].prod : |
467 | if (prod) | 442 | gp10b_slcg_pwr_csb[i].disable; |
468 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | 443 | gk20a_writel(g, reg, val); |
469 | gp10b_slcg_pwr_csb[i].prod); | 444 | } |
470 | else | ||
471 | gk20a_writel(g, gp10b_slcg_pwr_csb[i].addr, | ||
472 | gp10b_slcg_pwr_csb[i].disable); | ||
473 | } | 445 | } |
474 | } | 446 | } |
475 | 447 | ||
@@ -477,18 +449,15 @@ void gp10b_slcg_pmu_load_gating_prod(struct gk20a *g, | |||
477 | bool prod) | 449 | bool prod) |
478 | { | 450 | { |
479 | u32 i; | 451 | u32 i; |
480 | u32 size = sizeof(gp10b_slcg_pmu) / sizeof(struct gating_desc); | 452 | u32 size = (u32)(sizeof(gp10b_slcg_pmu) / GATING_DESC_SIZE); |
481 | 453 | ||
482 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 454 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
483 | return; | 455 | for (i = 0; i < size; i++) { |
484 | 456 | u32 reg = gp10b_slcg_pmu[i].addr; | |
485 | for (i = 0; i < size; i++) { | 457 | u32 val = prod ? gp10b_slcg_pmu[i].prod : |
486 | if (prod) | 458 | gp10b_slcg_pmu[i].disable; |
487 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | 459 | gk20a_writel(g, reg, val); |
488 | gp10b_slcg_pmu[i].prod); | 460 | } |
489 | else | ||
490 | gk20a_writel(g, gp10b_slcg_pmu[i].addr, | ||
491 | gp10b_slcg_pmu[i].disable); | ||
492 | } | 461 | } |
493 | } | 462 | } |
494 | 463 | ||
@@ -496,18 +465,15 @@ void gp10b_slcg_therm_load_gating_prod(struct gk20a *g, | |||
496 | bool prod) | 465 | bool prod) |
497 | { | 466 | { |
498 | u32 i; | 467 | u32 i; |
499 | u32 size = sizeof(gp10b_slcg_therm) / sizeof(struct gating_desc); | 468 | u32 size = (u32)(sizeof(gp10b_slcg_therm) / GATING_DESC_SIZE); |
500 | 469 | ||
501 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 470 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
502 | return; | 471 | for (i = 0; i < size; i++) { |
503 | 472 | u32 reg = gp10b_slcg_therm[i].addr; | |
504 | for (i = 0; i < size; i++) { | 473 | u32 val = prod ? gp10b_slcg_therm[i].prod : |
505 | if (prod) | 474 | gp10b_slcg_therm[i].disable; |
506 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | 475 | gk20a_writel(g, reg, val); |
507 | gp10b_slcg_therm[i].prod); | 476 | } |
508 | else | ||
509 | gk20a_writel(g, gp10b_slcg_therm[i].addr, | ||
510 | gp10b_slcg_therm[i].disable); | ||
511 | } | 477 | } |
512 | } | 478 | } |
513 | 479 | ||
@@ -515,18 +481,15 @@ void gp10b_slcg_xbar_load_gating_prod(struct gk20a *g, | |||
515 | bool prod) | 481 | bool prod) |
516 | { | 482 | { |
517 | u32 i; | 483 | u32 i; |
518 | u32 size = sizeof(gp10b_slcg_xbar) / sizeof(struct gating_desc); | 484 | u32 size = (u32)(sizeof(gp10b_slcg_xbar) / GATING_DESC_SIZE); |
519 | 485 | ||
520 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) | 486 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) { |
521 | return; | 487 | for (i = 0; i < size; i++) { |
522 | 488 | u32 reg = gp10b_slcg_xbar[i].addr; | |
523 | for (i = 0; i < size; i++) { | 489 | u32 val = prod ? gp10b_slcg_xbar[i].prod : |
524 | if (prod) | 490 | gp10b_slcg_xbar[i].disable; |
525 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | 491 | gk20a_writel(g, reg, val); |
526 | gp10b_slcg_xbar[i].prod); | 492 | } |
527 | else | ||
528 | gk20a_writel(g, gp10b_slcg_xbar[i].addr, | ||
529 | gp10b_slcg_xbar[i].disable); | ||
530 | } | 493 | } |
531 | } | 494 | } |
532 | 495 | ||
@@ -534,18 +497,15 @@ void gp10b_blcg_bus_load_gating_prod(struct gk20a *g, | |||
534 | bool prod) | 497 | bool prod) |
535 | { | 498 | { |
536 | u32 i; | 499 | u32 i; |
537 | u32 size = sizeof(gp10b_blcg_bus) / sizeof(struct gating_desc); | 500 | u32 size = (u32)(sizeof(gp10b_blcg_bus) / GATING_DESC_SIZE); |
538 | 501 | ||
539 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 502 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
540 | return; | 503 | for (i = 0; i < size; i++) { |
541 | 504 | u32 reg = gp10b_blcg_bus[i].addr; | |
542 | for (i = 0; i < size; i++) { | 505 | u32 val = prod ? gp10b_blcg_bus[i].prod : |
543 | if (prod) | 506 | gp10b_blcg_bus[i].disable; |
544 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | 507 | gk20a_writel(g, reg, val); |
545 | gp10b_blcg_bus[i].prod); | 508 | } |
546 | else | ||
547 | gk20a_writel(g, gp10b_blcg_bus[i].addr, | ||
548 | gp10b_blcg_bus[i].disable); | ||
549 | } | 509 | } |
550 | } | 510 | } |
551 | 511 | ||
@@ -553,18 +513,15 @@ void gp10b_blcg_ce_load_gating_prod(struct gk20a *g, | |||
553 | bool prod) | 513 | bool prod) |
554 | { | 514 | { |
555 | u32 i; | 515 | u32 i; |
556 | u32 size = sizeof(gp10b_blcg_ce) / sizeof(struct gating_desc); | 516 | u32 size = (u32)(sizeof(gp10b_blcg_ce) / GATING_DESC_SIZE); |
557 | 517 | ||
558 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 518 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
559 | return; | 519 | for (i = 0; i < size; i++) { |
560 | 520 | u32 reg = gp10b_blcg_ce[i].addr; | |
561 | for (i = 0; i < size; i++) { | 521 | u32 val = prod ? gp10b_blcg_ce[i].prod : |
562 | if (prod) | 522 | gp10b_blcg_ce[i].disable; |
563 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | 523 | gk20a_writel(g, reg, val); |
564 | gp10b_blcg_ce[i].prod); | 524 | } |
565 | else | ||
566 | gk20a_writel(g, gp10b_blcg_ce[i].addr, | ||
567 | gp10b_blcg_ce[i].disable); | ||
568 | } | 525 | } |
569 | } | 526 | } |
570 | 527 | ||
@@ -572,18 +529,15 @@ void gp10b_blcg_ctxsw_firmware_load_gating_prod(struct gk20a *g, | |||
572 | bool prod) | 529 | bool prod) |
573 | { | 530 | { |
574 | u32 i; | 531 | u32 i; |
575 | u32 size = sizeof(gp10b_blcg_ctxsw_prog) / sizeof(struct gating_desc); | 532 | u32 size = (u32)(sizeof(gp10b_blcg_ctxsw_prog) / GATING_DESC_SIZE); |
576 | 533 | ||
577 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 534 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
578 | return; | 535 | for (i = 0; i < size; i++) { |
579 | 536 | u32 reg = gp10b_blcg_ctxsw_prog[i].addr; | |
580 | for (i = 0; i < size; i++) { | 537 | u32 val = prod ? gp10b_blcg_ctxsw_prog[i].prod : |
581 | if (prod) | 538 | gp10b_blcg_ctxsw_prog[i].disable; |
582 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | 539 | gk20a_writel(g, reg, val); |
583 | gp10b_blcg_ctxsw_prog[i].prod); | 540 | } |
584 | else | ||
585 | gk20a_writel(g, gp10b_blcg_ctxsw_prog[i].addr, | ||
586 | gp10b_blcg_ctxsw_prog[i].disable); | ||
587 | } | 541 | } |
588 | } | 542 | } |
589 | 543 | ||
@@ -591,18 +545,15 @@ void gp10b_blcg_fb_load_gating_prod(struct gk20a *g, | |||
591 | bool prod) | 545 | bool prod) |
592 | { | 546 | { |
593 | u32 i; | 547 | u32 i; |
594 | u32 size = sizeof(gp10b_blcg_fb) / sizeof(struct gating_desc); | 548 | u32 size = (u32)(sizeof(gp10b_blcg_fb) / GATING_DESC_SIZE); |
595 | 549 | ||
596 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 550 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
597 | return; | 551 | for (i = 0; i < size; i++) { |
598 | 552 | u32 reg = gp10b_blcg_fb[i].addr; | |
599 | for (i = 0; i < size; i++) { | 553 | u32 val = prod ? gp10b_blcg_fb[i].prod : |
600 | if (prod) | 554 | gp10b_blcg_fb[i].disable; |
601 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | 555 | gk20a_writel(g, reg, val); |
602 | gp10b_blcg_fb[i].prod); | 556 | } |
603 | else | ||
604 | gk20a_writel(g, gp10b_blcg_fb[i].addr, | ||
605 | gp10b_blcg_fb[i].disable); | ||
606 | } | 557 | } |
607 | } | 558 | } |
608 | 559 | ||
@@ -610,18 +561,15 @@ void gp10b_blcg_fifo_load_gating_prod(struct gk20a *g, | |||
610 | bool prod) | 561 | bool prod) |
611 | { | 562 | { |
612 | u32 i; | 563 | u32 i; |
613 | u32 size = sizeof(gp10b_blcg_fifo) / sizeof(struct gating_desc); | 564 | u32 size = (u32)(sizeof(gp10b_blcg_fifo) / GATING_DESC_SIZE); |
614 | |||
615 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | ||
616 | return; | ||
617 | 565 | ||
566 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
618 | for (i = 0; i < size; i++) { | 567 | for (i = 0; i < size; i++) { |
619 | if (prod) | 568 | u32 reg = gp10b_blcg_fifo[i].addr; |
620 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | 569 | u32 val = prod ? gp10b_blcg_fifo[i].prod : |
621 | gp10b_blcg_fifo[i].prod); | 570 | gp10b_blcg_fifo[i].disable; |
622 | else | 571 | gk20a_writel(g, reg, val); |
623 | gk20a_writel(g, gp10b_blcg_fifo[i].addr, | 572 | } |
624 | gp10b_blcg_fifo[i].disable); | ||
625 | } | 573 | } |
626 | } | 574 | } |
627 | 575 | ||
@@ -629,18 +577,15 @@ void gp10b_blcg_gr_load_gating_prod(struct gk20a *g, | |||
629 | bool prod) | 577 | bool prod) |
630 | { | 578 | { |
631 | u32 i; | 579 | u32 i; |
632 | u32 size = sizeof(gp10b_blcg_gr) / sizeof(struct gating_desc); | 580 | u32 size = (u32)(sizeof(gp10b_blcg_gr) / GATING_DESC_SIZE); |
633 | 581 | ||
634 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 582 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
635 | return; | 583 | for (i = 0; i < size; i++) { |
636 | 584 | u32 reg = gp10b_blcg_gr[i].addr; | |
637 | for (i = 0; i < size; i++) { | 585 | u32 val = prod ? gp10b_blcg_gr[i].prod : |
638 | if (prod) | 586 | gp10b_blcg_gr[i].disable; |
639 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | 587 | gk20a_writel(g, reg, val); |
640 | gp10b_blcg_gr[i].prod); | 588 | } |
641 | else | ||
642 | gk20a_writel(g, gp10b_blcg_gr[i].addr, | ||
643 | gp10b_blcg_gr[i].disable); | ||
644 | } | 589 | } |
645 | } | 590 | } |
646 | 591 | ||
@@ -648,18 +593,15 @@ void gp10b_blcg_ltc_load_gating_prod(struct gk20a *g, | |||
648 | bool prod) | 593 | bool prod) |
649 | { | 594 | { |
650 | u32 i; | 595 | u32 i; |
651 | u32 size = sizeof(gp10b_blcg_ltc) / sizeof(struct gating_desc); | 596 | u32 size = (u32)(sizeof(gp10b_blcg_ltc) / GATING_DESC_SIZE); |
652 | 597 | ||
653 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 598 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
654 | return; | 599 | for (i = 0; i < size; i++) { |
655 | 600 | u32 reg = gp10b_blcg_ltc[i].addr; | |
656 | for (i = 0; i < size; i++) { | 601 | u32 val = prod ? gp10b_blcg_ltc[i].prod : |
657 | if (prod) | 602 | gp10b_blcg_ltc[i].disable; |
658 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | 603 | gk20a_writel(g, reg, val); |
659 | gp10b_blcg_ltc[i].prod); | 604 | } |
660 | else | ||
661 | gk20a_writel(g, gp10b_blcg_ltc[i].addr, | ||
662 | gp10b_blcg_ltc[i].disable); | ||
663 | } | 605 | } |
664 | } | 606 | } |
665 | 607 | ||
@@ -667,18 +609,15 @@ void gp10b_blcg_pwr_csb_load_gating_prod(struct gk20a *g, | |||
667 | bool prod) | 609 | bool prod) |
668 | { | 610 | { |
669 | u32 i; | 611 | u32 i; |
670 | u32 size = sizeof(gp10b_blcg_pwr_csb) / sizeof(struct gating_desc); | 612 | u32 size = (u32)(sizeof(gp10b_blcg_pwr_csb) / GATING_DESC_SIZE); |
671 | 613 | ||
672 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 614 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
673 | return; | 615 | for (i = 0; i < size; i++) { |
674 | 616 | u32 reg = gp10b_blcg_pwr_csb[i].addr; | |
675 | for (i = 0; i < size; i++) { | 617 | u32 val = prod ? gp10b_blcg_pwr_csb[i].prod : |
676 | if (prod) | 618 | gp10b_blcg_pwr_csb[i].disable; |
677 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | 619 | gk20a_writel(g, reg, val); |
678 | gp10b_blcg_pwr_csb[i].prod); | 620 | } |
679 | else | ||
680 | gk20a_writel(g, gp10b_blcg_pwr_csb[i].addr, | ||
681 | gp10b_blcg_pwr_csb[i].disable); | ||
682 | } | 621 | } |
683 | } | 622 | } |
684 | 623 | ||
@@ -686,18 +625,15 @@ void gp10b_blcg_pmu_load_gating_prod(struct gk20a *g, | |||
686 | bool prod) | 625 | bool prod) |
687 | { | 626 | { |
688 | u32 i; | 627 | u32 i; |
689 | u32 size = sizeof(gp10b_blcg_pmu) / sizeof(struct gating_desc); | 628 | u32 size = (u32)(sizeof(gp10b_blcg_pmu) / GATING_DESC_SIZE); |
690 | 629 | ||
691 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 630 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
692 | return; | 631 | for (i = 0; i < size; i++) { |
693 | 632 | u32 reg = gp10b_blcg_pmu[i].addr; | |
694 | for (i = 0; i < size; i++) { | 633 | u32 val = prod ? gp10b_blcg_pmu[i].prod : |
695 | if (prod) | 634 | gp10b_blcg_pmu[i].disable; |
696 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | 635 | gk20a_writel(g, reg, val); |
697 | gp10b_blcg_pmu[i].prod); | 636 | } |
698 | else | ||
699 | gk20a_writel(g, gp10b_blcg_pmu[i].addr, | ||
700 | gp10b_blcg_pmu[i].disable); | ||
701 | } | 637 | } |
702 | } | 638 | } |
703 | 639 | ||
@@ -705,18 +641,15 @@ void gp10b_blcg_xbar_load_gating_prod(struct gk20a *g, | |||
705 | bool prod) | 641 | bool prod) |
706 | { | 642 | { |
707 | u32 i; | 643 | u32 i; |
708 | u32 size = sizeof(gp10b_blcg_xbar) / sizeof(struct gating_desc); | 644 | u32 size = (u32)(sizeof(gp10b_blcg_xbar) / GATING_DESC_SIZE); |
709 | 645 | ||
710 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 646 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
711 | return; | 647 | for (i = 0; i < size; i++) { |
712 | 648 | u32 reg = gp10b_blcg_xbar[i].addr; | |
713 | for (i = 0; i < size; i++) { | 649 | u32 val = prod ? gp10b_blcg_xbar[i].prod : |
714 | if (prod) | 650 | gp10b_blcg_xbar[i].disable; |
715 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | 651 | gk20a_writel(g, reg, val); |
716 | gp10b_blcg_xbar[i].prod); | 652 | } |
717 | else | ||
718 | gk20a_writel(g, gp10b_blcg_xbar[i].addr, | ||
719 | gp10b_blcg_xbar[i].disable); | ||
720 | } | 653 | } |
721 | } | 654 | } |
722 | 655 | ||
@@ -724,19 +657,14 @@ void gr_gp10b_pg_gr_load_gating_prod(struct gk20a *g, | |||
724 | bool prod) | 657 | bool prod) |
725 | { | 658 | { |
726 | u32 i; | 659 | u32 i; |
727 | u32 size = sizeof(gp10b_pg_gr) / sizeof(struct gating_desc); | 660 | u32 size = (u32)(sizeof(gp10b_pg_gr) / GATING_DESC_SIZE); |
728 | 661 | ||
729 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) | 662 | if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { |
730 | return; | 663 | for (i = 0; i < size; i++) { |
731 | 664 | u32 reg = gp10b_pg_gr[i].addr; | |
732 | for (i = 0; i < size; i++) { | 665 | u32 val = prod ? gp10b_pg_gr[i].prod : |
733 | if (prod) | 666 | gp10b_pg_gr[i].disable; |
734 | gk20a_writel(g, gp10b_pg_gr[i].addr, | 667 | gk20a_writel(g, reg, val); |
735 | gp10b_pg_gr[i].prod); | 668 | } |
736 | else | ||
737 | gk20a_writel(g, gp10b_pg_gr[i].addr, | ||
738 | gp10b_pg_gr[i].disable); | ||
739 | } | 669 | } |
740 | } | 670 | } |
741 | |||
742 | #endif /* __gp10b_gating_reglist_h__ */ | ||