diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-05-24 16:00:14 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:07 -0400 |
commit | dbb8792baf2142626728abf909fb201144b9b56a (patch) | |
tree | 6ca5edfeb3f757bef86aaf6d6ebbf12b2c2aa748 /drivers/gpu/nvgpu/common/bus | |
parent | ed65f1f26e2d0ca4a491215297b61d25b0c1493b (diff) |
gpu: nvgpu: Move setting of BAR0_WINDOW to bus
Move setting of BAR0_WINDOW to bus HAL. Also moves the usage of spinlock to
common code so that pramin_gk20a.[ch] can be deleted.
JIRA NVGPU-588
Change-Id: I3ceabc56016711b2c93f31fedf07daa778a4873a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730890
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/common/bus')
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/bus/bus_gk20a.h | 8 |
2 files changed, 38 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c index 62dd7450..a2c6a3d7 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c | |||
@@ -169,3 +169,34 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
169 | 169 | ||
170 | return 0; | 170 | return 0; |
171 | } | 171 | } |
172 | |||
173 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, | ||
174 | struct nvgpu_sgt *sgt, struct nvgpu_sgl *sgl, u32 w) | ||
175 | { | ||
176 | u64 bufbase = nvgpu_sgt_get_phys(g, sgt, sgl); | ||
177 | u64 addr = bufbase + w * sizeof(u32); | ||
178 | u32 hi = (u32)((addr & ~(u64)0xfffff) | ||
179 | >> bus_bar0_window_target_bar0_window_base_shift_v()); | ||
180 | u32 lo = (u32)(addr & 0xfffff); | ||
181 | u32 win = nvgpu_aperture_mask(g, mem, | ||
182 | bus_bar0_window_target_sys_mem_noncoherent_f(), | ||
183 | bus_bar0_window_target_sys_mem_coherent_f(), | ||
184 | bus_bar0_window_target_vid_mem_f()) | | ||
185 | bus_bar0_window_base_f(hi); | ||
186 | |||
187 | nvgpu_log(g, gpu_dbg_mem, | ||
188 | "0x%08x:%08x begin for %p,%p at [%llx,%llx] (sz %llx)", | ||
189 | hi, lo, mem, sgl, bufbase, | ||
190 | bufbase + nvgpu_sgt_get_phys(g, sgt, sgl), | ||
191 | nvgpu_sgt_get_length(sgt, sgl)); | ||
192 | |||
193 | WARN_ON(!bufbase); | ||
194 | |||
195 | if (g->mm.pramin_window != win) { | ||
196 | gk20a_writel(g, bus_bar0_window_r(), win); | ||
197 | gk20a_readl(g, bus_bar0_window_r()); | ||
198 | g->mm.pramin_window = win; | ||
199 | } | ||
200 | |||
201 | return lo; | ||
202 | } | ||
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h index 1f81a4b0..fe1cad58 100644 --- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h +++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h | |||
@@ -27,10 +27,16 @@ | |||
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct gpu_ops; | 28 | struct gpu_ops; |
29 | struct nvgpu_mem; | 29 | struct nvgpu_mem; |
30 | struct nvgpu_sgt; | ||
31 | struct nvgpu_sgl; | ||
30 | 32 | ||
31 | void gk20a_bus_isr(struct gk20a *g); | 33 | void gk20a_bus_isr(struct gk20a *g); |
32 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); | 34 | int gk20a_read_ptimer(struct gk20a *g, u64 *value); |
33 | void gk20a_bus_init_hw(struct gk20a *g); | 35 | void gk20a_bus_init_hw(struct gk20a *g); |
34 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); | 36 | int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst); |
37 | u32 gk20a_bus_set_bar0_window(struct gk20a *g, struct nvgpu_mem *mem, | ||
38 | struct nvgpu_sgt *sgt, | ||
39 | struct nvgpu_sgl *sgl, | ||
40 | u32 w); | ||
35 | 41 | ||
36 | #endif /* GK20A_H */ | 42 | #endif /* BUS_GK20A_H */ |