gpu: nvgpu: fix error for static code analysis

use memset to fill structures with zero instead of
assigning zero.
mark functions local to the file as static
fixing errors in clk, perf and therm modules.

Bug 200299572

Change-Id: I0470298803c35b6faed2edc2a0c1dbf0e47e842e
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1472940
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

4 files changed, 28 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index 8b36394d..c1b8d5e1 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -49,15 +49,19 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload)
 {
         struct pmu_cmd cmd;
         struct pmu_msg msg;
-        struct pmu_payload payload = { {0} };
+        struct pmu_payload payload;
         u32 status;
         u32 seqdesc;
-        struct nv_pmu_clk_rpc rpccall = {0};
-        struct clkrpc_pmucmdhandler_params handler = {0};
+        struct nv_pmu_clk_rpc rpccall;
+        struct clkrpc_pmucmdhandler_params handler;
         struct nv_pmu_clk_load *clkload;
         struct clk_freq_controllers *pclk_freq_controllers;
         struct ctrl_boardobjgrp_mask_e32 *load_mask;
 
+        memset(&payload, 0, sizeof(struct pmu_payload));
+        memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+        memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
         pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers;
         rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
         clkload = &rpccall.params.clk_load;
@@ -120,13 +124,17 @@ u32 clk_pmu_vin_load(struct gk20a *g)
 {
         struct pmu_cmd cmd;
         struct pmu_msg msg;
-        struct pmu_payload payload = { {0} };
+        struct pmu_payload payload;
         u32 status;
         u32 seqdesc;
-        struct nv_pmu_clk_rpc rpccall = {0};
-        struct clkrpc_pmucmdhandler_params handler = {0};
+        struct nv_pmu_clk_rpc rpccall;
+        struct clkrpc_pmucmdhandler_params handler;
         struct nv_pmu_clk_load *clkload;
 
+        memset(&payload, 0, sizeof(struct pmu_payload));
+        memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+        memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
         rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
         clkload = &rpccall.params.clk_load;
         clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
@@ -179,13 +187,17 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
 {
         struct pmu_cmd cmd;
         struct pmu_msg msg;
-        struct pmu_payload payload = { {0} };
+        struct pmu_payload payload;
         u32 status;
         u32 seqdesc;
-        struct nv_pmu_clk_rpc rpccall = {0};
-        struct clkrpc_pmucmdhandler_params handler = {0};
+        struct nv_pmu_clk_rpc rpccall;
+        struct clkrpc_pmucmdhandler_params handler;
         struct nv_pmu_clk_vf_change_inject *vfchange;
 
+        memset(&payload, 0, sizeof(struct pmu_payload));
+        memset(&rpccall, 0, sizeof(struct nv_pmu_clk_rpc));
+        memset(&handler, 0, sizeof(struct clkrpc_pmucmdhandler_params));
+
         if ((setfllclk->gpc2clkmhz == 0) || (setfllclk->xbar2clkmhz == 0) ||
                 (setfllclk->sys2clkmhz == 0) || (setfllclk->voltuv == 0))
                 return -EINVAL;
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c
index c784bdb4..84ce7371 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/clk/clk_domain.c
@@ -31,7 +31,8 @@ static u32 devinit_get_clocks_table(struct gk20a *g,
 static u32 clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
         *board_obj_ptr, struct nv_pmu_boardobj *ppmudata);
 
-const struct vbios_clocks_table_1x_hal_clock_entry vbiosclktbl1xhalentry[] = {
+static const struct vbios_clocks_table_1x_hal_clock_entry
+                vbiosclktbl1xhalentry[] = {
         { clkwhich_gpc2clk,    true,  },
         { clkwhich_xbar2clk,   true,  },
         { clkwhich_mclk,       false, },
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
index 61c8b81b..632d7b35 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
@@ -144,7 +144,8 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g,
         return status;
 }
 
-struct clk_freq_controller *clk_clk_freq_controller_construct(struct gk20a *g,
+static struct clk_freq_controller *clk_clk_freq_controller_construct(
+        struct gk20a *g,
         void *pargs)
 {
         struct boardobj *board_obj_ptr = NULL;
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c
index 690f8681..cf04c98c 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.c
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.c
@@ -2262,7 +2262,7 @@ fail_mclk_mutex:
 int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
 {
         struct clk_mclk_state *mclk;
-        struct pmu_payload payload = { {0} };
+        struct pmu_payload payload;
         struct nv_pmu_seq_cmd cmd;
         struct nv_pmu_seq_cmd_run_script *pseq_cmd;
         u32 seqdesc;
@@ -2277,6 +2277,8 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val)
 
         gk20a_dbg_info("");
 
+        memset(&payload, 0, sizeof(struct pmu_payload));
+
         mclk = &g->clk_pmu.clk_mclk;
 
         nvgpu_mutex_acquire(&mclk->mclk_lock);