diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-07-04 01:55:00 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 03:39:21 -0400 |
commit | e808d345f11885453fc65862ec4e3dd4a375ff6d (patch) | |
tree | ccc3bb1ade5ff991ca1805084b76f154ca9736ee /drivers/gpu/nvgpu/clk | |
parent | 2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (diff) |
gpu: nvgpu: rename gk20a_pmu_cmd_post()
- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post()
- replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post()
wherever called.
JIRA NVGPU-93
Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1512904
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 72b6d246..494a09cf 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -97,7 +97,7 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload) | |||
97 | 97 | ||
98 | handler.prpccall = &rpccall; | 98 | handler.prpccall = &rpccall; |
99 | handler.success = 0; | 99 | handler.success = 0; |
100 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 100 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
101 | PMU_COMMAND_QUEUE_LPQ, | 101 | PMU_COMMAND_QUEUE_LPQ, |
102 | clkrpc_pmucmdhandler, (void *)&handler, | 102 | clkrpc_pmucmdhandler, (void *)&handler, |
103 | &seqdesc, ~0); | 103 | &seqdesc, ~0); |
@@ -160,7 +160,7 @@ u32 clk_pmu_vin_load(struct gk20a *g) | |||
160 | 160 | ||
161 | handler.prpccall = &rpccall; | 161 | handler.prpccall = &rpccall; |
162 | handler.success = 0; | 162 | handler.success = 0; |
163 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 163 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
164 | PMU_COMMAND_QUEUE_LPQ, | 164 | PMU_COMMAND_QUEUE_LPQ, |
165 | clkrpc_pmucmdhandler, (void *)&handler, | 165 | clkrpc_pmucmdhandler, (void *)&handler, |
166 | &seqdesc, ~0); | 166 | &seqdesc, ~0); |
@@ -262,7 +262,7 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) | |||
262 | handler.prpccall = &rpccall; | 262 | handler.prpccall = &rpccall; |
263 | handler.success = 0; | 263 | handler.success = 0; |
264 | 264 | ||
265 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload, | 265 | status = nvgpu_pmu_cmd_post(g, &cmd, NULL, &payload, |
266 | PMU_COMMAND_QUEUE_LPQ, | 266 | PMU_COMMAND_QUEUE_LPQ, |
267 | clkrpc_pmucmdhandler, (void *)&handler, | 267 | clkrpc_pmucmdhandler, (void *)&handler, |
268 | &seqdesc, ~0); | 268 | &seqdesc, ~0); |