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authorVaikundanathan S <vaikuns@nvidia.com>2018-07-13 05:54:04 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-10 18:22:48 -0400
commita02e1c1f0b012b743d4c1ba9c853057b4359107e (patch)
tree32e9e5f5533ecb90a4f376a086249255df0e7b6b /drivers/gpu/nvgpu/clk
parent4f01d6a9b9a54cf6042db157de0d40965077f6a2 (diff)
nvgpu:ps35: Clock domain changes
1. PMU interface changes 2. Split PS3.0 and PS3.5 into two dev init functions. 3. Split construct and pmu_data_init to two funcitons. 4. Fixing GV100 impact on PS3.5 changes Change-Id: I46ba80325d4a249918edbe4cf868ddf47c778aa1 Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1777739 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.h1
-rw-r--r--drivers/gpu/nvgpu/clk/clk_domain.c556
-rw-r--r--drivers/gpu/nvgpu/clk/clk_domain.h25
3 files changed, 531 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index afff6963..0a0d9c98 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -89,6 +89,7 @@ struct vbios_clock_domain {
89struct vbios_clocks_table_1x_hal_clock_entry { 89struct vbios_clocks_table_1x_hal_clock_entry {
90 enum nv_pmu_clk_clkwhich domain; 90 enum nv_pmu_clk_clkwhich domain;
91 bool b_noise_aware_capable; 91 bool b_noise_aware_capable;
92 u8 clk_vf_curve_count;
92}; 93};
93 94
94#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0 95#define NV_PERF_HEADER_4X_CLOCKS_DOMAINS_4_GPC2CLK 0
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c
index c0445e5c..1fccff54 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/clk/clk_domain.c
@@ -41,15 +41,15 @@ static int clk_domain_pmudatainit_super(struct gk20a *g, struct boardobj
41 41
42static struct vbios_clocks_table_1x_hal_clock_entry 42static struct vbios_clocks_table_1x_hal_clock_entry
43 vbiosclktbl1xhalentry_gp[] = { 43 vbiosclktbl1xhalentry_gp[] = {
44 { clkwhich_gpc2clk, true, }, 44 { clkwhich_gpc2clk, true, 1, },
45 { clkwhich_xbar2clk, true, }, 45 { clkwhich_xbar2clk, true, 1, },
46 { clkwhich_mclk, false, }, 46 { clkwhich_mclk, false, 1, },
47 { clkwhich_sys2clk, true, }, 47 { clkwhich_sys2clk, true, 1, },
48 { clkwhich_hub2clk, false, }, 48 { clkwhich_hub2clk, false, 1, },
49 { clkwhich_nvdclk, false, }, 49 { clkwhich_nvdclk, false, 1, },
50 { clkwhich_pwrclk, false, }, 50 { clkwhich_pwrclk, false, 1, },
51 { clkwhich_dispclk, false, }, 51 { clkwhich_dispclk, false, 1, },
52 { clkwhich_pciegenclk, false, } 52 { clkwhich_pciegenclk, false, 1, }
53}; 53};
54/* 54/*
55 * Updated from RM devinit_clock.c 55 * Updated from RM devinit_clock.c
@@ -58,16 +58,16 @@ static struct vbios_clocks_table_1x_hal_clock_entry
58 */ 58 */
59static struct vbios_clocks_table_1x_hal_clock_entry 59static struct vbios_clocks_table_1x_hal_clock_entry
60 vbiosclktbl1xhalentry_gv[] = { 60 vbiosclktbl1xhalentry_gv[] = {
61 { clkwhich_gpcclk, true, }, 61 { clkwhich_gpcclk, true, 2, },
62 { clkwhich_xbarclk, true, }, 62 { clkwhich_xbarclk, true, 1, },
63 { clkwhich_mclk, false, }, 63 { clkwhich_mclk, false, 1, },
64 { clkwhich_sysclk, true, }, 64 { clkwhich_sysclk, true, 1, },
65 { clkwhich_hubclk, false, }, 65 { clkwhich_hubclk, false, 1, },
66 { clkwhich_nvdclk, true, }, 66 { clkwhich_nvdclk, true, 1, },
67 { clkwhich_pwrclk, false, }, 67 { clkwhich_pwrclk, false, 1, },
68 { clkwhich_dispclk, false, }, 68 { clkwhich_dispclk, false, 1, },
69 { clkwhich_pciegenclk, false, }, 69 { clkwhich_pciegenclk, false, 1, },
70 { clkwhich_hostclk, true, } 70 { clkwhich_hostclk, true, 1, }
71}; 71};
72 72
73static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains) 73static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains)
@@ -300,11 +300,216 @@ int clk_domain_pmu_setup(struct gk20a *g)
300 return status; 300 return status;
301} 301}
302 302
303static int devinit_get_clocks_table(struct gk20a *g, 303static int devinit_get_clocks_table_35(struct gk20a *g,
304 struct clk_domains *pclkdomainobjs) 304 struct clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
305{
306 int status = 0;
307 struct vbios_clocks_table_35_header clocks_table_header = { 0 };
308 struct vbios_clocks_table_35_entry clocks_table_entry = { 0 };
309 struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry;
310 u8 *clocks_tbl_entry_ptr = NULL;
311 u32 index = 0;
312 struct clk_domain *pclkdomain_dev;
313 union {
314 struct boardobj boardobj;
315 struct clk_domain clk_domain;
316 struct clk_domain_3x v3x;
317 struct clk_domain_3x_fixed v3x_fixed;
318 struct clk_domain_35_prog v35_prog;
319 struct clk_domain_35_master v35_master;
320 struct clk_domain_35_slave v35_slave;
321 } clk_domain_data;
322
323 nvgpu_log_info(g, " ");
324
325 memcpy(&clocks_table_header, clocks_table_ptr,
326 VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09);
327 if (clocks_table_header.header_size <
328 (u8) VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09) {
329 status = -EINVAL;
330 goto done;
331 }
332
333 if (clocks_table_header.entry_size <
334 (u8) VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11) {
335 status = -EINVAL;
336 goto done;
337 }
338
339 switch (clocks_table_header.clocks_hal) {
340 case CLK_TABLE_HAL_ENTRY_GP:
341 {
342 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gp;
343 break;
344 }
345 case CLK_TABLE_HAL_ENTRY_GV:
346 {
347 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gv;
348 break;
349 }
350 default:
351 {
352 status = -EINVAL;
353 goto done;
354 }
355 }
356
357 pclkdomainobjs->cntr_sampling_periodms =
358 (u16)clocks_table_header.cntr_sampling_periodms;
359
360 /* Read table entries*/
361 clocks_tbl_entry_ptr = clocks_table_ptr +
362 clocks_table_header.header_size;
363 for (index = 0; index < clocks_table_header.entry_count; index++) {
364 memcpy((void*) &clocks_table_entry, (void*) clocks_tbl_entry_ptr,
365 clocks_table_header.entry_size);
366 clk_domain_data.clk_domain.domain =
367 (u8) vbiosclktbl1xhalentry[index].domain;
368 clk_domain_data.clk_domain.api_domain =
369 clktranslatehalmumsettoapinumset(
370 (u32) BIT(clk_domain_data.clk_domain.domain));
371 clk_domain_data.v3x.b_noise_aware_capable =
372 vbiosclktbl1xhalentry[index].b_noise_aware_capable;
373
374 switch (BIOS_GET_FIELD(clocks_table_entry.flags0,
375 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE)) {
376 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED:
377 {
378 clk_domain_data.boardobj.type =
379 CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED;
380 clk_domain_data.v3x_fixed.freq_mhz = (u16)BIOS_GET_FIELD(
381 clocks_table_entry.param1,
382 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ);
383 break;
384 }
385
386 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER:
387 {
388 clk_domain_data.boardobj.type =
389 CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER;
390 clk_domain_data.v35_prog.super.clk_prog_idx_first =
391 (u8)(BIOS_GET_FIELD(clocks_table_entry.param0,
392 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST));
393 clk_domain_data.v35_prog.super.clk_prog_idx_last =
394 (u8)(BIOS_GET_FIELD(clocks_table_entry.param0,
395 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST));
396 clk_domain_data.v35_prog.super.noise_unaware_ordering_index =
397 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
398 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX));
399 if (clk_domain_data.v3x.b_noise_aware_capable) {
400 clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering =
401 (bool)(BIOS_GET_FIELD(clocks_table_entry.param2,
402 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING));
403
404 } else {
405 clk_domain_data.v35_prog.super.noise_aware_ordering_index =
406 CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID;
407 clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = false;
408 }
409 clk_domain_data.v35_prog.pre_volt_ordering_index =
410 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
411 NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX));
412
413 clk_domain_data.v35_prog.post_volt_ordering_index =
414 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
415 NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX));
416
417 clk_domain_data.v35_prog.super.factory_delta.data.delta_khz = 0;
418 clk_domain_data.v35_prog.super.factory_delta.type = 0;
419
420 clk_domain_data.v35_prog.super.freq_delta_min_mhz =
421 (u16)(BIOS_GET_FIELD(clocks_table_entry.param1,
422 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MIN_MHZ));
423
424 clk_domain_data.v35_prog.super.freq_delta_max_mhz =
425 (u16)(BIOS_GET_FIELD(clocks_table_entry.param1,
426 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ));
427 clk_domain_data.v35_prog.clk_vf_curve_count =
428 vbiosclktbl1xhalentry[index].clk_vf_curve_count;
429 break;
430 }
431
432 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE:
433 {
434 clk_domain_data.boardobj.type =
435 CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE;
436 clk_domain_data.v35_prog.super.clk_prog_idx_first =
437 (u8)(BIOS_GET_FIELD(clocks_table_entry.param0,
438 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_FIRST));
439 clk_domain_data.v35_prog.super.clk_prog_idx_last =
440 (u8)(BIOS_GET_FIELD(clocks_table_entry.param0,
441 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM0_PROG_CLK_PROG_IDX_LAST));
442 clk_domain_data.v35_prog.super.noise_unaware_ordering_index =
443 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
444 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_NOISE_UNAWARE_ORDERING_IDX));
445
446 if (clk_domain_data.v3x.b_noise_aware_capable) {
447 clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering =
448 (bool)(BIOS_GET_FIELD(clocks_table_entry.param2,
449 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM2_PROG_FORCE_NOISE_UNAWARE_ORDERING));
450
451 } else {
452 clk_domain_data.v35_prog.super.noise_aware_ordering_index =
453 CTRL_CLK_CLK_DOMAIN_3X_PROG_ORDERING_INDEX_INVALID;
454 clk_domain_data.v35_prog.super.b_force_noise_unaware_ordering = false;
455 }
456 clk_domain_data.v35_prog.pre_volt_ordering_index =
457 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
458 NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_PRE_VOLT_ORDERING_IDX));
459
460 clk_domain_data.v35_prog.post_volt_ordering_index =
461 (u8)(BIOS_GET_FIELD(clocks_table_entry.param2,
462 NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM2_PROG_POST_VOLT_ORDERING_IDX));
463
464 clk_domain_data.v35_prog.super.factory_delta.data.delta_khz = 0;
465 clk_domain_data.v35_prog.super.factory_delta.type = 0;
466 clk_domain_data.v35_prog.super.freq_delta_min_mhz = 0;
467 clk_domain_data.v35_prog.super.freq_delta_max_mhz = 0;
468 clk_domain_data.v35_slave.slave.master_idx =
469 (u8)(BIOS_GET_FIELD(clocks_table_entry.param1,
470 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN));
471 break;
472 }
473
474 default:
475 {
476 nvgpu_err(g,
477 "error reading clock domain entry %d", index);
478 status = -EINVAL;
479 goto done;
480 }
481
482 }
483 pclkdomain_dev = construct_clk_domain(g,
484 (void *)&clk_domain_data);
485 if (pclkdomain_dev == NULL) {
486 nvgpu_err(g,
487 "unable to construct clock domain boardobj for %d",
488 index);
489 status = -EINVAL;
490 goto done;
491 }
492 status = boardobjgrp_objinsert(
493 &pclkdomainobjs->super.super,
494 (struct boardobj *)(void*) pclkdomain_dev, index);
495 if (status != 0UL) {
496 nvgpu_err(g,
497 "unable to insert clock domain boardobj for %d", index);
498 status = (u32) -EINVAL;
499 goto done;
500 }
501 clocks_tbl_entry_ptr += clocks_table_header.entry_size;
502 }
503
504done:
505 nvgpu_log_info(g, " done status %x", status);
506 return status;
507}
508
509static int devinit_get_clocks_table_1x(struct gk20a *g,
510 struct clk_domains *pclkdomainobjs, u8 *clocks_table_ptr)
305{ 511{
306 int status = 0; 512 int status = 0;
307 u8 *clocks_table_ptr = NULL;
308 struct vbios_clocks_table_1x_header clocks_table_header = { 0 }; 513 struct vbios_clocks_table_1x_header clocks_table_header = { 0 };
309 struct vbios_clocks_table_1x_entry clocks_table_entry = { 0 }; 514 struct vbios_clocks_table_1x_entry clocks_table_entry = { 0 };
310 struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry; 515 struct vbios_clocks_table_1x_hal_clock_entry *vbiosclktbl1xhalentry;
@@ -323,38 +528,37 @@ static int devinit_get_clocks_table(struct gk20a *g,
323 528
324 nvgpu_log_info(g, " "); 529 nvgpu_log_info(g, " ");
325 530
326 clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
327 g->bios.clock_token, CLOCKS_TABLE);
328 if (clocks_table_ptr == NULL) {
329 status = -EINVAL;
330 goto done;
331 }
332
333 memcpy(&clocks_table_header, clocks_table_ptr, 531 memcpy(&clocks_table_header, clocks_table_ptr,
334 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07); 532 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07);
335 if (clocks_table_header.header_size < 533 if (clocks_table_header.header_size <
336 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07) { 534 (u8) VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07) {
337 status = -EINVAL; 535 status = -EINVAL;
338 goto done; 536 goto done;
339 } 537 }
340 538
341 if (clocks_table_header.entry_size < 539 if (clocks_table_header.entry_size <
342 VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09) { 540 (u8) VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09) {
343 status = -EINVAL; 541 status = -EINVAL;
344 goto done; 542 goto done;
345 } 543 }
346 544
347 switch (clocks_table_header.clocks_hal) { 545 switch (clocks_table_header.clocks_hal) {
348 case CLK_TABLE_HAL_ENTRY_GP: 546 case CLK_TABLE_HAL_ENTRY_GP:
547 {
349 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gp; 548 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gp;
350 break; 549 break;
550 }
351 case CLK_TABLE_HAL_ENTRY_GV: 551 case CLK_TABLE_HAL_ENTRY_GV:
552 {
352 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gv; 553 vbiosclktbl1xhalentry = vbiosclktbl1xhalentry_gv;
353 break; 554 break;
555 }
354 default: 556 default:
557 {
355 status = -EINVAL; 558 status = -EINVAL;
356 goto done; 559 goto done;
357 } 560 }
561 }
358 562
359 pclkdomainobjs->cntr_sampling_periodms = 563 pclkdomainobjs->cntr_sampling_periodms =
360 (u16)clocks_table_header.cntr_sampling_periodms; 564 (u16)clocks_table_header.cntr_sampling_periodms;
@@ -363,10 +567,10 @@ static int devinit_get_clocks_table(struct gk20a *g,
363 clocks_tbl_entry_ptr = clocks_table_ptr + 567 clocks_tbl_entry_ptr = clocks_table_ptr +
364 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07; 568 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07;
365 for (index = 0; index < clocks_table_header.entry_count; index++) { 569 for (index = 0; index < clocks_table_header.entry_count; index++) {
366 memcpy(&clocks_table_entry, clocks_tbl_entry_ptr, 570 memcpy((void*) &clocks_table_entry, (void*) clocks_tbl_entry_ptr,
367 clocks_table_header.entry_size); 571 clocks_table_header.entry_size);
368 clk_domain_data.clk_domain.domain = 572 clk_domain_data.clk_domain.domain =
369 vbiosclktbl1xhalentry[index].domain; 573 (u8) vbiosclktbl1xhalentry[index].domain;
370 clk_domain_data.clk_domain.api_domain = 574 clk_domain_data.clk_domain.api_domain =
371 clktranslatehalmumsettoapinumset( 575 clktranslatehalmumsettoapinumset(
372 BIT(clk_domain_data.clk_domain.domain)); 576 BIT(clk_domain_data.clk_domain.domain));
@@ -376,14 +580,17 @@ static int devinit_get_clocks_table(struct gk20a *g,
376 switch (BIOS_GET_FIELD(clocks_table_entry.flags0, 580 switch (BIOS_GET_FIELD(clocks_table_entry.flags0,
377 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE)) { 581 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE)) {
378 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED: 582 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_FIXED:
583 {
379 clk_domain_data.boardobj.type = 584 clk_domain_data.boardobj.type =
380 CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED; 585 CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED;
381 clk_domain_data.v3x_fixed.freq_mhz = (u16)BIOS_GET_FIELD( 586 clk_domain_data.v3x_fixed.freq_mhz = (u16)BIOS_GET_FIELD(
382 clocks_table_entry.param1, 587 clocks_table_entry.param1,
383 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ); 588 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_FIXED_FREQUENCY_MHZ);
384 break; 589 break;
590 }
385 591
386 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER: 592 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_MASTER:
593 {
387 clk_domain_data.boardobj.type = 594 clk_domain_data.boardobj.type =
388 CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER; 595 CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER;
389 clk_domain_data.v3x_prog.clk_prog_idx_first = 596 clk_domain_data.v3x_prog.clk_prog_idx_first =
@@ -419,8 +626,10 @@ static int devinit_get_clocks_table(struct gk20a *g,
419 (u16)(BIOS_GET_FIELD(clocks_table_entry.param1, 626 (u16)(BIOS_GET_FIELD(clocks_table_entry.param1,
420 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ)); 627 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_MASTER_FREQ_OC_DELTA_MAX_MHZ));
421 break; 628 break;
629 }
422 630
423 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE: 631 case NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_FLAGS0_USAGE_SLAVE:
632 {
424 clk_domain_data.boardobj.type = 633 clk_domain_data.boardobj.type =
425 CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE; 634 CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE;
426 clk_domain_data.v3x_prog.clk_prog_idx_first = 635 clk_domain_data.v3x_prog.clk_prog_idx_first =
@@ -453,12 +662,15 @@ static int devinit_get_clocks_table(struct gk20a *g,
453 (u8)(BIOS_GET_FIELD(clocks_table_entry.param1, 662 (u8)(BIOS_GET_FIELD(clocks_table_entry.param1,
454 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN)); 663 NV_VBIOS_CLOCKS_TABLE_1X_ENTRY_PARAM1_SLAVE_MASTER_DOMAIN));
455 break; 664 break;
665 }
456 666
457 default: 667 default:
668 {
458 nvgpu_err(g, 669 nvgpu_err(g,
459 "error reading clock domain entry %d", index); 670 "error reading clock domain entry %d", index);
460 status = -EINVAL; 671 status = (u32) -EINVAL;
461 goto done; 672 goto done;
673 }
462 674
463 } 675 }
464 pclkdomain_dev = construct_clk_domain(g, 676 pclkdomain_dev = construct_clk_domain(g,
@@ -467,15 +679,15 @@ static int devinit_get_clocks_table(struct gk20a *g,
467 nvgpu_err(g, 679 nvgpu_err(g,
468 "unable to construct clock domain boardobj for %d", 680 "unable to construct clock domain boardobj for %d",
469 index); 681 index);
470 status = -EINVAL; 682 status = (u32) -EINVAL;
471 goto done; 683 goto done;
472 } 684 }
473 status = boardobjgrp_objinsert(&pclkdomainobjs->super.super, 685 status = boardobjgrp_objinsert(&pclkdomainobjs->super.super,
474 (struct boardobj *)pclkdomain_dev, index); 686 (struct boardobj *)(void *)pclkdomain_dev, index);
475 if (status) { 687 if (status != 0UL) {
476 nvgpu_err(g, 688 nvgpu_err(g,
477 "unable to insert clock domain boardobj for %d", index); 689 "unable to insert clock domain boardobj for %d", index);
478 status = -EINVAL; 690 status = (u32) -EINVAL;
479 goto done; 691 goto done;
480 } 692 }
481 clocks_tbl_entry_ptr += clocks_table_header.entry_size; 693 clocks_tbl_entry_ptr += clocks_table_header.entry_size;
@@ -486,6 +698,33 @@ done:
486 return status; 698 return status;
487} 699}
488 700
701static int devinit_get_clocks_table(struct gk20a *g,
702 struct clk_domains *pclkdomainobjs)
703{
704 int status = 0;
705 u8 *clocks_table_ptr = NULL;
706 struct vbios_clocks_table_1x_header clocks_table_header = { 0 };
707 nvgpu_log_info(g, " ");
708
709 clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
710 g->bios.clock_token, CLOCKS_TABLE);
711 if (clocks_table_ptr == NULL) {
712 status = -EINVAL;
713 goto done;
714 }
715 memcpy(&clocks_table_header, clocks_table_ptr,
716 VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07);
717 if (clocks_table_header.version == 0x35U) {
718 devinit_get_clocks_table_35(g, pclkdomainobjs, clocks_table_ptr);
719 }
720 else {
721 devinit_get_clocks_table_1x(g, pclkdomainobjs, clocks_table_ptr);
722 }
723 done:
724 return status;
725
726}
727
489static int clkdomainclkproglink_not_supported(struct gk20a *g, 728static int clkdomainclkproglink_not_supported(struct gk20a *g,
490 struct clk_pmupstate *pclk, 729 struct clk_pmupstate *pclk,
491 struct clk_domain *pdomain) 730 struct clk_domain *pdomain)
@@ -822,13 +1061,53 @@ done:
822 return status; 1061 return status;
823} 1062}
824 1063
1064static int clk_domain_pmudatainit_35_prog(struct gk20a *g,
1065 struct boardobj *board_obj_ptr,
1066 struct nv_pmu_boardobj *ppmudata)
1067{
1068 int status = 0;
1069 struct clk_domain_35_prog *pclk_domain_35_prog;
1070 struct clk_domain_3x_prog *pclk_domain_3x_prog;
1071 struct nv_pmu_clk_clk_domain_35_prog_boardobj_set *pset;
1072 struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs);
1073
1074 nvgpu_log_info(g, " ");
1075
1076 status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata);
1077 if (status != 0UL) {
1078 return status;
1079 }
1080
1081 pclk_domain_35_prog = (struct clk_domain_35_prog *)(void*)board_obj_ptr;
1082 pclk_domain_3x_prog = &pclk_domain_35_prog->super;
1083
1084 pset = (struct nv_pmu_clk_clk_domain_35_prog_boardobj_set *)
1085 (void*) ppmudata;
1086
1087 pset->super.clk_prog_idx_first = pclk_domain_3x_prog->clk_prog_idx_first;
1088 pset->super.clk_prog_idx_last = pclk_domain_3x_prog->clk_prog_idx_last;
1089 pset->super.b_force_noise_unaware_ordering =
1090 pclk_domain_3x_prog->b_force_noise_unaware_ordering;
1091 pset->super.factory_delta = pclk_domain_3x_prog->factory_delta;
1092 pset->super.freq_delta_min_mhz = pclk_domain_3x_prog->freq_delta_min_mhz;
1093 pset->super.freq_delta_max_mhz = pclk_domain_3x_prog->freq_delta_max_mhz;
1094 memcpy(&pset->super.deltas, &pdomains->deltas,
1095 (sizeof(struct ctrl_clk_clk_delta)));
1096 pset->pre_volt_ordering_index = pclk_domain_35_prog->pre_volt_ordering_index;
1097 pset->post_volt_ordering_index = pclk_domain_35_prog->post_volt_ordering_index;
1098 pset->clk_pos = pclk_domain_35_prog->clk_pos;
1099 pset->clk_vf_curve_count = pclk_domain_35_prog->clk_vf_curve_count;
1100
1101 return status;
1102}
1103
825static int _clk_domain_pmudatainit_3x_prog(struct gk20a *g, 1104static int _clk_domain_pmudatainit_3x_prog(struct gk20a *g,
826 struct boardobj *board_obj_ptr, 1105 struct boardobj *board_obj_ptr,
827 struct nv_pmu_boardobj *ppmudata) 1106 struct nv_pmu_boardobj *ppmudata)
828{ 1107{
829 int status = 0; 1108 int status = 0;
830 struct clk_domain_3x_prog *pclk_domain_3x_prog; 1109 struct clk_domain_3x_prog *pclk_domain_3x_prog;
831 struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set *pset; 1110 struct nv_pmu_clk_clk_domain_30_prog_boardobj_set *pset;
832 struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs); 1111 struct clk_domains *pdomains = &(g->clk_pmu.clk_domainobjs);
833 1112
834 nvgpu_log_info(g, " "); 1113 nvgpu_log_info(g, " ");
@@ -840,26 +1119,76 @@ static int _clk_domain_pmudatainit_3x_prog(struct gk20a *g,
840 1119
841 pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr; 1120 pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr;
842 1121
843 pset = (struct nv_pmu_clk_clk_domain_3x_prog_boardobj_set *) 1122 pset = (struct nv_pmu_clk_clk_domain_30_prog_boardobj_set *)
844 ppmudata; 1123 ppmudata;
845 1124
846 pset->clk_prog_idx_first = pclk_domain_3x_prog->clk_prog_idx_first; 1125 pset->super.clk_prog_idx_first = pclk_domain_3x_prog->clk_prog_idx_first;
847 pset->clk_prog_idx_last = pclk_domain_3x_prog->clk_prog_idx_last; 1126 pset->super.clk_prog_idx_last = pclk_domain_3x_prog->clk_prog_idx_last;
848 pset->noise_unaware_ordering_index = 1127 pset->noise_unaware_ordering_index =
849 pclk_domain_3x_prog->noise_unaware_ordering_index; 1128 pclk_domain_3x_prog->noise_unaware_ordering_index;
850 pset->noise_aware_ordering_index = 1129 pset->noise_aware_ordering_index =
851 pclk_domain_3x_prog->noise_aware_ordering_index; 1130 pclk_domain_3x_prog->noise_aware_ordering_index;
852 pset->b_force_noise_unaware_ordering = 1131 pset->super.b_force_noise_unaware_ordering =
853 pclk_domain_3x_prog->b_force_noise_unaware_ordering; 1132 pclk_domain_3x_prog->b_force_noise_unaware_ordering;
854 pset->factory_delta = pclk_domain_3x_prog->factory_delta; 1133 pset->super.factory_delta = pclk_domain_3x_prog->factory_delta;
855 pset->freq_delta_min_mhz = pclk_domain_3x_prog->freq_delta_min_mhz; 1134 pset->super.freq_delta_min_mhz = pclk_domain_3x_prog->freq_delta_min_mhz;
856 pset->freq_delta_max_mhz = pclk_domain_3x_prog->freq_delta_max_mhz; 1135 pset->super.freq_delta_max_mhz = pclk_domain_3x_prog->freq_delta_max_mhz;
857 memcpy(&pset->deltas, &pdomains->deltas, 1136 memcpy(&pset->super.deltas, &pdomains->deltas,
858 (sizeof(struct ctrl_clk_clk_delta))); 1137 (sizeof(struct ctrl_clk_clk_delta)));
859 1138
860 return status; 1139 return status;
861} 1140}
862 1141
1142static int clk_domain_construct_35_prog(struct gk20a *g,
1143 struct boardobj **ppboardobj,
1144 u16 size, void *pargs)
1145{
1146 struct boardobj *ptmpobj = (struct boardobj *)pargs;
1147 struct clk_domain_35_prog *pdomain;
1148 struct clk_domain_35_prog *ptmpdomain =
1149 (struct clk_domain_35_prog *)pargs;
1150 int status = 0;
1151
1152 ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG);
1153 status = clk_domain_construct_3x(g, ppboardobj, size, pargs);
1154 if (status != 0UL)
1155 {
1156 return (u32) -EINVAL;
1157 }
1158
1159 pdomain = (struct clk_domain_35_prog *)(void*) *ppboardobj;
1160
1161 pdomain->super.super.super.super.pmudatainit =
1162 clk_domain_pmudatainit_35_prog;
1163
1164 pdomain->super.super.super.clkdomainclkproglink =
1165 clkdomainclkproglink_3x_prog;
1166
1167 pdomain->super.super.super.clkdomainclkvfsearch =
1168 clkdomainvfsearch;
1169
1170 pdomain->super.super.super.clkdomainclkgetfpoints =
1171 clkdomaingetfpoints;
1172
1173 pdomain->super.clk_prog_idx_first = ptmpdomain->super.clk_prog_idx_first;
1174 pdomain->super.clk_prog_idx_last = ptmpdomain->super.clk_prog_idx_last;
1175 pdomain->super.noise_unaware_ordering_index =
1176 ptmpdomain->super.noise_unaware_ordering_index;
1177 pdomain->super.noise_aware_ordering_index =
1178 ptmpdomain->super.noise_aware_ordering_index;
1179 pdomain->super.b_force_noise_unaware_ordering =
1180 ptmpdomain->super.b_force_noise_unaware_ordering;
1181 pdomain->super.factory_delta = ptmpdomain->super.factory_delta;
1182 pdomain->super.freq_delta_min_mhz = ptmpdomain->super.freq_delta_min_mhz;
1183 pdomain->super.freq_delta_max_mhz = ptmpdomain->super.freq_delta_max_mhz;
1184 pdomain->pre_volt_ordering_index = ptmpdomain->pre_volt_ordering_index;
1185 pdomain->post_volt_ordering_index = ptmpdomain->post_volt_ordering_index;
1186 pdomain->clk_pos = ptmpdomain->clk_pos;
1187 pdomain->clk_vf_curve_count = ptmpdomain->clk_vf_curve_count;
1188
1189 return status;
1190}
1191
863static int clk_domain_construct_3x_prog(struct gk20a *g, 1192static int clk_domain_construct_3x_prog(struct gk20a *g,
864 struct boardobj **ppboardobj, 1193 struct boardobj **ppboardobj,
865 u16 size, void *pargs) 1194 u16 size, void *pargs)
@@ -905,7 +1234,32 @@ static int clk_domain_construct_3x_prog(struct gk20a *g,
905 return status; 1234 return status;
906} 1235}
907 1236
908static int _clk_domain_pmudatainit_3x_slave(struct gk20a *g, 1237static int _clk_domain_pmudatainit_35_slave(struct gk20a *g,
1238 struct boardobj *board_obj_ptr,
1239 struct nv_pmu_boardobj *ppmudata)
1240{
1241 int status = 0;
1242 struct clk_domain_35_slave *pclk_domain_35_slave;
1243 struct nv_pmu_clk_clk_domain_35_slave_boardobj_set *pset;
1244
1245 nvgpu_log_info(g, " ");
1246
1247 status = clk_domain_pmudatainit_35_prog(g, board_obj_ptr, ppmudata);
1248 if (status != 0UL) {
1249 return status;
1250 }
1251
1252 pclk_domain_35_slave = (struct clk_domain_35_slave *)(void*)board_obj_ptr;
1253
1254 pset = (struct nv_pmu_clk_clk_domain_35_slave_boardobj_set *)
1255 (void*) ppmudata;
1256
1257 pset->slave.master_idx = pclk_domain_35_slave->slave.master_idx;
1258
1259 return status;
1260}
1261
1262static int clk_domain_pmudatainit_3x_slave(struct gk20a *g,
909 struct boardobj *board_obj_ptr, 1263 struct boardobj *board_obj_ptr,
910 struct nv_pmu_boardobj *ppmudata) 1264 struct nv_pmu_boardobj *ppmudata)
911{ 1265{
@@ -930,6 +1284,39 @@ static int _clk_domain_pmudatainit_3x_slave(struct gk20a *g,
930 return status; 1284 return status;
931} 1285}
932 1286
1287static int clk_domain_construct_35_slave(struct gk20a *g,
1288 struct boardobj **ppboardobj,
1289 u16 size, void *pargs)
1290{
1291 struct boardobj *ptmpobj = (struct boardobj *)pargs;
1292 struct clk_domain_35_slave *pdomain;
1293 struct clk_domain_35_slave *ptmpdomain =
1294 (struct clk_domain_35_slave *)pargs;
1295 int status = 0;
1296
1297 if (BOARDOBJ_GET_TYPE(pargs) != (u8) CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE) {
1298 return (u32) -EINVAL;
1299 }
1300
1301 ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE);
1302 status = clk_domain_construct_35_prog(g, ppboardobj, size, pargs);
1303 if (status != 0UL) {
1304 return (u32) -EINVAL;
1305 }
1306
1307 pdomain = (struct clk_domain_35_slave *)(void*)*ppboardobj;
1308
1309 pdomain->super.super.super.super.super.pmudatainit =
1310 _clk_domain_pmudatainit_35_slave;
1311
1312 pdomain->slave.master_idx = ptmpdomain->slave.master_idx;
1313
1314 pdomain->slave.clkdomainclkgetslaveclk =
1315 clkdomaingetslaveclk;
1316
1317 return status;
1318}
1319
933static int clk_domain_construct_3x_slave(struct gk20a *g, 1320static int clk_domain_construct_3x_slave(struct gk20a *g,
934 struct boardobj **ppboardobj, 1321 struct boardobj **ppboardobj,
935 u16 size, void *pargs) 1322 u16 size, void *pargs)
@@ -940,20 +1327,20 @@ static int clk_domain_construct_3x_slave(struct gk20a *g,
940 (struct clk_domain_3x_slave *)pargs; 1327 (struct clk_domain_3x_slave *)pargs;
941 int status = 0; 1328 int status = 0;
942 1329
943 if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) { 1330 if (BOARDOBJ_GET_TYPE(pargs) != (u8) CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) {
944 return -EINVAL; 1331 return -EINVAL;
945 } 1332 }
946 1333
947 ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE); 1334 ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE);
948 status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); 1335 status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs);
949 if (status) { 1336 if (status != 0UL) {
950 return -EINVAL; 1337 return -EINVAL;
951 } 1338 }
952 1339
953 pdomain = (struct clk_domain_3x_slave *)*ppboardobj; 1340 pdomain = (struct clk_domain_3x_slave *)*ppboardobj;
954 1341
955 pdomain->super.super.super.super.pmudatainit = 1342 pdomain->super.super.super.super.pmudatainit =
956 _clk_domain_pmudatainit_3x_slave; 1343 clk_domain_pmudatainit_3x_slave;
957 1344
958 pdomain->master_idx = ptmpdomain->master_idx; 1345 pdomain->master_idx = ptmpdomain->master_idx;
959 1346
@@ -1007,6 +1394,32 @@ done:
1007 return status; 1394 return status;
1008} 1395}
1009 1396
1397static int clk_domain_pmudatainit_35_master(struct gk20a *g,
1398 struct boardobj *board_obj_ptr,
1399 struct nv_pmu_boardobj *ppmudata)
1400{
1401 int status = 0;
1402 struct clk_domain_35_master *pclk_domain_35_master;
1403 struct nv_pmu_clk_clk_domain_35_master_boardobj_set *pset;
1404
1405 nvgpu_log_info(g, " ");
1406
1407 status = clk_domain_pmudatainit_35_prog(g, board_obj_ptr, ppmudata);
1408 if (status != 0UL) {
1409 return status;
1410 }
1411
1412 pclk_domain_35_master = (struct clk_domain_35_master *)
1413 (void*) board_obj_ptr;
1414
1415 pset = (struct nv_pmu_clk_clk_domain_35_master_boardobj_set *)
1416 (void*) ppmudata;
1417
1418 pset->master.slave_idxs_mask = pclk_domain_35_master->master.slave_idxs_mask;
1419
1420 return status;
1421}
1422
1010static int _clk_domain_pmudatainit_3x_master(struct gk20a *g, 1423static int _clk_domain_pmudatainit_3x_master(struct gk20a *g,
1011 struct boardobj *board_obj_ptr, 1424 struct boardobj *board_obj_ptr,
1012 struct nv_pmu_boardobj *ppmudata) 1425 struct nv_pmu_boardobj *ppmudata)
@@ -1032,6 +1445,36 @@ static int _clk_domain_pmudatainit_3x_master(struct gk20a *g,
1032 return status; 1445 return status;
1033} 1446}
1034 1447
1448static int clk_domain_construct_35_master(struct gk20a *g,
1449 struct boardobj **ppboardobj,
1450 u16 size, void *pargs)
1451{
1452 struct boardobj *ptmpobj = (struct boardobj *)pargs;
1453 struct clk_domain_35_master *pdomain;
1454 int status = 0;
1455
1456 if (BOARDOBJ_GET_TYPE(pargs) != (u8) CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER) {
1457 return -EINVAL;
1458 }
1459
1460 ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER);
1461 status = clk_domain_construct_35_prog(g, ppboardobj, size, pargs);
1462 if (status != 0UL) {
1463 return (u32) -EINVAL;
1464 }
1465
1466 pdomain = (struct clk_domain_35_master *)(void*) *ppboardobj;
1467
1468 pdomain->super.super.super.super.super.pmudatainit =
1469 clk_domain_pmudatainit_35_master;
1470 pdomain->super.super.super.super.clkdomainclkproglink =
1471 clkdomainclkproglink_3x_master;
1472
1473 pdomain->master.slave_idxs_mask = 0;
1474
1475 return status;
1476}
1477
1035static int clk_domain_construct_3x_master(struct gk20a *g, 1478static int clk_domain_construct_3x_master(struct gk20a *g,
1036 struct boardobj **ppboardobj, 1479 struct boardobj **ppboardobj,
1037 u16 size, void *pargs) 1480 u16 size, void *pargs)
@@ -1140,11 +1583,22 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs)
1140 sizeof(struct clk_domain_3x_fixed), pargs); 1583 sizeof(struct clk_domain_3x_fixed), pargs);
1141 break; 1584 break;
1142 1585
1586 case CTRL_CLK_CLK_DOMAIN_TYPE_35_MASTER:
1587 status = clk_domain_construct_35_master(g, &board_obj_ptr,
1588 sizeof(struct clk_domain_35_master), pargs);
1589 break;
1590
1591
1143 case CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER: 1592 case CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER:
1144 status = clk_domain_construct_3x_master(g, &board_obj_ptr, 1593 status = clk_domain_construct_3x_master(g, &board_obj_ptr,
1145 sizeof(struct clk_domain_3x_master), pargs); 1594 sizeof(struct clk_domain_3x_master), pargs);
1146 break; 1595 break;
1147 1596
1597 case CTRL_CLK_CLK_DOMAIN_TYPE_35_SLAVE:
1598 status = clk_domain_construct_35_slave(g, &board_obj_ptr,
1599 sizeof(struct clk_domain_35_slave), pargs);
1600 break;
1601
1148 case CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE: 1602 case CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE:
1149 status = clk_domain_construct_3x_slave(g, &board_obj_ptr, 1603 status = clk_domain_construct_3x_slave(g, &board_obj_ptr,
1150 sizeof(struct clk_domain_3x_slave), pargs); 1604 sizeof(struct clk_domain_3x_slave), pargs);
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h
index d0170339..a8ae0d48 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.h
+++ b/drivers/gpu/nvgpu/clk/clk_domain.h
@@ -112,17 +112,42 @@ struct clk_domain_3x_prog {
112 u8 noise_aware_ordering_index; 112 u8 noise_aware_ordering_index;
113}; 113};
114 114
115struct clk_domain_35_prog {
116 struct clk_domain_3x_prog super;
117 u8 pre_volt_ordering_index;
118 u8 post_volt_ordering_index;
119 u8 clk_pos;
120 u8 clk_vf_curve_count;
121};
122
115struct clk_domain_3x_master { 123struct clk_domain_3x_master {
116 struct clk_domain_3x_prog super; 124 struct clk_domain_3x_prog super;
117 u32 slave_idxs_mask; 125 u32 slave_idxs_mask;
118}; 126};
119 127
128struct clk_domain_35_master {
129 struct clk_domain_35_prog super;
130 struct clk_domain_3x_master master;
131 struct boardobjgrpmask_e32 master_slave_domains_grp_mask;
132};
133
120struct clk_domain_3x_slave { 134struct clk_domain_3x_slave {
121 struct clk_domain_3x_prog super; 135 struct clk_domain_3x_prog super;
122 u8 master_idx; 136 u8 master_idx;
123 clkgetslaveclk *clkdomainclkgetslaveclk; 137 clkgetslaveclk *clkdomainclkgetslaveclk;
124}; 138};
125 139
140struct clk_domain_30_slave {
141 u8 rsvd;
142 u8 master_idx;
143 clkgetslaveclk *clkdomainclkgetslaveclk;
144};
145
146struct clk_domain_35_slave {
147 struct clk_domain_35_prog super;
148 struct clk_domain_30_slave slave;
149};
150
126int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk); 151int clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
127 152
128#define CLK_CLK_DOMAIN_GET(pclk, idx) \ 153#define CLK_CLK_DOMAIN_GET(pclk, idx) \
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 20:59:12 -0400