diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-09-21 05:32:59 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:50 -0500 |
commit | 741d78ec45f6c48348743617ba5ae7163c95e49a (patch) | |
tree | af51c25cd2ccae6ced16710d80209e35181b3b8f /drivers/gpu/nvgpu/clk | |
parent | 173bdefc92e2e4ef8f1e7e6ead7f86e746bee935 (diff) |
gpu: nvgpu: construct/load tabels & set voltage
- Read voltage tables from VBIOS & construct
then send to PMU.
- compare & set voltage based on
mclk/gpc2clk clk, take higher voltage
between two & set.
JIRA DNVGPU-122
Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224365
(cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c)
Reviewed-on: http://git-master/r/1244657
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.h | 3 |
3 files changed, 34 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index 918cd43c..ce071018 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -17,8 +17,12 @@ | |||
17 | #include "pmuif/gpmuifvolt.h" | 17 | #include "pmuif/gpmuifvolt.h" |
18 | #include "ctrl/ctrlclk.h" | 18 | #include "ctrl/ctrlclk.h" |
19 | #include "ctrl/ctrlvolt.h" | 19 | #include "ctrl/ctrlvolt.h" |
20 | #include "volt/volt.h" | ||
20 | #include "gk20a/pmu_gk20a.h" | 21 | #include "gk20a/pmu_gk20a.h" |
21 | 22 | ||
23 | #define BOOT_GPC2CLK_MHZ 2581 | ||
24 | #define BOOT_MCLK_MHZ 3003 | ||
25 | |||
22 | struct clkrpc_pmucmdhandler_params { | 26 | struct clkrpc_pmucmdhandler_params { |
23 | struct nv_pmu_clk_rpc *prpccall; | 27 | struct nv_pmu_clk_rpc *prpccall; |
24 | u32 success; | 28 | u32 success; |
@@ -382,15 +386,38 @@ int clk_set_boot_fll_clk(struct gk20a *g) | |||
382 | { | 386 | { |
383 | int status; | 387 | int status; |
384 | struct change_fll_clk bootfllclk; | 388 | struct change_fll_clk bootfllclk; |
389 | u16 gpc2clk_clkmhz = BOOT_GPC2CLK_MHZ; | ||
390 | u32 gpc2clk_voltuv = 0; | ||
391 | u16 mclk_clkmhz = BOOT_MCLK_MHZ; | ||
392 | u32 mclk_voltuv = 0; | ||
393 | u32 voltuv = 0; | ||
385 | 394 | ||
386 | mutex_init(&g->clk_pmu.changeclkmutex); | 395 | mutex_init(&g->clk_pmu.changeclkmutex); |
387 | 396 | ||
397 | clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPC2CLK, &gpc2clk_clkmhz, | ||
398 | &gpc2clk_voltuv); | ||
399 | clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_MCLK, &mclk_clkmhz, | ||
400 | &mclk_voltuv); | ||
401 | |||
402 | voltuv = ((gpc2clk_voltuv) > (mclk_voltuv)) ? (gpc2clk_voltuv) | ||
403 | : (mclk_voltuv); | ||
404 | |||
405 | status = volt_set_voltage(g, voltuv, voltuv); | ||
406 | if (status) | ||
407 | gk20a_err(dev_from_gk20a(g), "attempt to set boot voltage failed %d", | ||
408 | voltuv); | ||
409 | |||
388 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; | 410 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPC2CLK; |
389 | bootfllclk.clkmhz = 2581; | 411 | bootfllclk.clkmhz = gpc2clk_clkmhz; |
390 | bootfllclk.voltuv = 825000; | 412 | bootfllclk.voltuv = voltuv; |
391 | status = clk_program_fllclks(g, &bootfllclk); | 413 | status = clk_program_fllclks(g, &bootfllclk); |
392 | if (status) | 414 | if (status) |
393 | gk20a_err(dev_from_gk20a(g), "attemp to set boot clk failed"); | 415 | gk20a_err(dev_from_gk20a(g), "attempt to set boot gpc2clk failed"); |
416 | |||
417 | status = g->clk_pmu.clk_mclk.change(g, DEFAULT_BOOT_MCLK_SPEED); | ||
418 | if (status) | ||
419 | gk20a_err(dev_from_gk20a(g), "attempt to set boot mclk failed"); | ||
420 | |||
394 | return status; | 421 | return status; |
395 | } | 422 | } |
396 | 423 | ||
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index b63fab1e..7b15767b 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c | |||
@@ -23,10 +23,6 @@ | |||
23 | 23 | ||
24 | #define VREG_COUNT 24 | 24 | #define VREG_COUNT 24 |
25 | 25 | ||
26 | #define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed | ||
27 | #define MCLK_LOW_SPEED_LIMIT 405 | ||
28 | #define MCLK_MID_SPEED_LIMIT 810 | ||
29 | |||
30 | struct memory_link_training_pattern { | 26 | struct memory_link_training_pattern { |
31 | u32 regaddr; | 27 | u32 regaddr; |
32 | u32 writeval; | 28 | u32 writeval; |
@@ -2220,7 +2216,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) | |||
2220 | 2216 | ||
2221 | mclk->init = true; | 2217 | mclk->init = true; |
2222 | 2218 | ||
2223 | return mclk->change(g, DEFAULT_BOOT_MCLK_SPEED); | 2219 | return 0; |
2224 | } | 2220 | } |
2225 | 2221 | ||
2226 | int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, enum gk20a_mclk_speed speed) | 2222 | int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, enum gk20a_mclk_speed speed) |
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h index edb7eb78..9d193c96 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.h +++ b/drivers/gpu/nvgpu/clk/clk_mclk.h | |||
@@ -22,6 +22,9 @@ enum gk20a_mclk_speed { | |||
22 | gk20a_mclk_high_speed, | 22 | gk20a_mclk_high_speed, |
23 | }; | 23 | }; |
24 | 24 | ||
25 | #define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed | ||
26 | #define MCLK_LOW_SPEED_LIMIT 405 | ||
27 | #define MCLK_MID_SPEED_LIMIT 810 | ||
25 | struct clk_mclk_state { | 28 | struct clk_mclk_state { |
26 | enum gk20a_mclk_speed speed; | 29 | enum gk20a_mclk_speed speed; |
27 | struct mutex mclk_mutex; | 30 | struct mutex mclk_mutex; |