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authorAlex Waterman <alexw@nvidia.com>2018-03-12 19:01:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-03-30 17:54:08 -0400
commit12cd49a733f88c2d6ad41a5c411d1076f26956ed (patch)
treec967b22b86c44165f1c61fbabb6a037dc30ec803 /drivers/gpu/nvgpu/clk
parent3d90f0aad537d92b42bc8250252f521b649077f8 (diff)
gpu: nvgpu: Cleanup more set but unused variables
This time they were largely located in the various common directories. JIRA NVGPU-525 Change-Id: I3a6d523b060a0c6761b227267890298c6d2fb19f Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1673820 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.c6
-rw-r--r--drivers/gpu/nvgpu/clk/clk_freq_controller.c3
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vf_point.c2
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vin.c4
4 files changed, 0 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
index 3906be48..ecc352b1 100644
--- a/drivers/gpu/nvgpu/clk/clk.c
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -58,7 +58,6 @@ static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
58int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx) 58int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
59{ 59{
60 struct pmu_cmd cmd; 60 struct pmu_cmd cmd;
61 struct pmu_msg msg;
62 struct pmu_payload payload; 61 struct pmu_payload payload;
63 u32 status; 62 u32 status;
64 u32 seqdesc; 63 u32 seqdesc;
@@ -122,7 +121,6 @@ int clk_pmu_freq_controller_load(struct gk20a *g, bool bload, u8 bit_idx)
122 (u32)sizeof(struct pmu_hdr); 121 (u32)sizeof(struct pmu_hdr);
123 122
124 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC; 123 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
125 msg.hdr.size = sizeof(struct pmu_msg);
126 124
127 payload.in.buf = (u8 *)&rpccall; 125 payload.in.buf = (u8 *)&rpccall;
128 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc); 126 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
@@ -163,7 +161,6 @@ done:
163u32 clk_pmu_vin_load(struct gk20a *g) 161u32 clk_pmu_vin_load(struct gk20a *g)
164{ 162{
165 struct pmu_cmd cmd; 163 struct pmu_cmd cmd;
166 struct pmu_msg msg;
167 struct pmu_payload payload; 164 struct pmu_payload payload;
168 u32 status; 165 u32 status;
169 u32 seqdesc; 166 u32 seqdesc;
@@ -185,7 +182,6 @@ u32 clk_pmu_vin_load(struct gk20a *g)
185 (u32)sizeof(struct pmu_hdr); 182 (u32)sizeof(struct pmu_hdr);
186 183
187 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC; 184 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
188 msg.hdr.size = sizeof(struct pmu_msg);
189 185
190 payload.in.buf = (u8 *)&rpccall; 186 payload.in.buf = (u8 *)&rpccall;
191 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc); 187 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
@@ -226,7 +222,6 @@ done:
226static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk) 222static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
227{ 223{
228 struct pmu_cmd cmd; 224 struct pmu_cmd cmd;
229 struct pmu_msg msg;
230 struct pmu_payload payload; 225 struct pmu_payload payload;
231 u32 status; 226 u32 status;
232 u32 seqdesc; 227 u32 seqdesc;
@@ -286,7 +281,6 @@ static u32 clk_pmu_vf_inject(struct gk20a *g, struct set_fll_clk *setfllclk)
286 (u32)sizeof(struct pmu_hdr); 281 (u32)sizeof(struct pmu_hdr);
287 282
288 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC; 283 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
289 msg.hdr.size = sizeof(struct pmu_msg);
290 284
291 payload.in.buf = (u8 *)&rpccall; 285 payload.in.buf = (u8 *)&rpccall;
292 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc); 286 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
index f5c1e929..fce177a7 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
@@ -180,7 +180,6 @@ static u32 clk_get_freq_controller_table(struct gk20a *g,
180 struct vbios_fct_1x_entry entry = { 0 }; 180 struct vbios_fct_1x_entry entry = { 0 };
181 u8 entry_idx; 181 u8 entry_idx;
182 u8 *entry_offset; 182 u8 *entry_offset;
183 u32 freq_controller_id;
184 struct clk_freq_controller *pclk_freq_cntr = NULL; 183 struct clk_freq_controller *pclk_freq_cntr = NULL;
185 struct clk_freq_controller *ptmp_freq_cntr = NULL; 184 struct clk_freq_controller *ptmp_freq_cntr = NULL;
186 struct clk_freq_controller_pi *ptmp_freq_cntr_pi = NULL; 185 struct clk_freq_controller_pi *ptmp_freq_cntr_pi = NULL;
@@ -233,8 +232,6 @@ static u32 clk_get_freq_controller_table(struct gk20a *g,
233 (u8)BIOS_GET_FIELD(entry.param0, 232 (u8)BIOS_GET_FIELD(entry.param0,
234 NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID); 233 NV_VBIOS_FCT_1X_ENTRY_PARAM0_ID);
235 234
236 freq_controller_id = ptmp_freq_cntr->controller_id;
237
238 pclk_domain = CLK_CLK_DOMAIN_GET((&g->clk_pmu), 235 pclk_domain = CLK_CLK_DOMAIN_GET((&g->clk_pmu),
239 (u32)entry.clk_domain_idx); 236 (u32)entry.clk_domain_idx);
240 freq_controller_data.freq_controller.clk_domain = 237 freq_controller_data.freq_controller.clk_domain =
diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c
index 49327698..0189bd8c 100644
--- a/drivers/gpu/nvgpu/clk/clk_vf_point.c
+++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c
@@ -93,7 +93,6 @@ u32 clk_vf_point_sw_setup(struct gk20a *g)
93{ 93{
94 u32 status; 94 u32 status;
95 struct boardobjgrp *pboardobjgrp = NULL; 95 struct boardobjgrp *pboardobjgrp = NULL;
96 struct clk_vf_points *pclkvfpointobjs;
97 96
98 gk20a_dbg_info(""); 97 gk20a_dbg_info("");
99 98
@@ -106,7 +105,6 @@ u32 clk_vf_point_sw_setup(struct gk20a *g)
106 } 105 }
107 106
108 pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super; 107 pboardobjgrp = &g->clk_pmu.clk_vf_pointobjs.super.super;
109 pclkvfpointobjs = &(g->clk_pmu.clk_vf_pointobjs);
110 108
111 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_VF_POINT); 109 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, CLK, CLK_VF_POINT);
112 110
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c
index 17e1c15a..6f47d2c8 100644
--- a/drivers/gpu/nvgpu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/clk/clk_vin.c
@@ -387,16 +387,12 @@ static u32 devinit_get_vin_device_table(struct gk20a *g,
387 /* Read table entries*/ 387 /* Read table entries*/
388 vin_tbl_entry_ptr = vin_table_ptr + vin_desc_table_header.header_sizee; 388 vin_tbl_entry_ptr = vin_table_ptr + vin_desc_table_header.header_sizee;
389 for (index = 0; index < vin_desc_table_header.entry_count; index++) { 389 for (index = 0; index < vin_desc_table_header.entry_count; index++) {
390 u32 vin_id;
391
392 memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr, 390 memcpy(&vin_desc_table_entry, vin_tbl_entry_ptr,
393 sizeof(struct vin_descriptor_entry_10)); 391 sizeof(struct vin_descriptor_entry_10));
394 392
395 if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED) 393 if (vin_desc_table_entry.vin_device_type == CTRL_CLK_VIN_TYPE_DISABLED)
396 continue; 394 continue;
397 395
398 vin_id = vin_desc_table_entry.vin_device_id;
399
400 vin_dev_data.super.type = 396 vin_dev_data.super.type =
401 (u8)vin_desc_table_entry.vin_device_type; 397 (u8)vin_desc_table_entry.vin_device_type;
402 vin_dev_data.id = (u8)vin_desc_table_entry.vin_device_id; 398 vin_dev_data.id = (u8)vin_desc_table_entry.vin_device_id;