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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-08-10 17:09:36 -0400
committerBo Yan <byan@nvidia.com>2018-08-20 14:00:59 -0400
commit227c6f7b7a499dd58e0db6859736cfe586ef0897 (patch)
treed354f8422647021693aefefa5124d865c29ecd32 /drivers/gpu/nvgpu/clk/clk_vin.c
parent9e69e0cf978b53706f55ffb873e3966b4bb3a7a8 (diff)
gpu: nvgpu: Move fuse HAL to common
Move implementation of fuse HAL to common/fuse. Also implements new fuse query functions for FBIO, FBP, TPC floorsweeping and security fuses. JIRA NVGPU-957 Change-Id: I55e256a4f1b59d50a721d4942907f70dc57467c4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1797177
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_vin.c')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vin.c200
1 files changed, 4 insertions, 196 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c
index 4e6fbe50..67eeffd5 100644
--- a/drivers/gpu/nvgpu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/clk/clk_vin.c
@@ -36,8 +36,6 @@
36#include "clk.h" 36#include "clk.h"
37#include "clk_vin.h" 37#include "clk_vin.h"
38 38
39#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
40
41static u32 devinit_get_vin_device_table(struct gk20a *g, 39static u32 devinit_get_vin_device_table(struct gk20a *g,
42 struct avfsvinobjs *pvinobjs); 40 struct avfsvinobjs *pvinobjs);
43 41
@@ -62,196 +60,6 @@ static u32 vin_device_init_pmudata_super(struct gk20a *g,
62 struct boardobj *board_obj_ptr, 60 struct boardobj *board_obj_ptr,
63 struct nv_pmu_boardobj *ppmudata); 61 struct nv_pmu_boardobj *ppmudata);
64 62
65static u32 read_vin_cal_fuse_rev(struct gk20a *g)
66{
67 return fuse_vin_cal_fuse_rev_data_v(
68 gk20a_readl(g, fuse_vin_cal_fuse_rev_r()));
69}
70
71static u32 read_vin_cal_slope_intercept_fuse(struct gk20a *g,
72 u32 vin_id, u32 *slope,
73 u32 *intercept)
74{
75 u32 data = 0;
76 u32 interceptdata = 0;
77 u32 slopedata = 0;
78 u32 gpc0data;
79 u32 gpc0slopedata;
80 u32 gpc0interceptdata;
81
82 /* read gpc0 irrespective of vin id */
83 gpc0data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
84 if (gpc0data == 0xFFFFFFFF)
85 return -EINVAL;
86
87 switch (vin_id) {
88 case CTRL_CLK_VIN_ID_GPC0:
89 break;
90
91 case CTRL_CLK_VIN_ID_GPC1:
92 data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
93 break;
94
95 case CTRL_CLK_VIN_ID_GPC2:
96 data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
97 break;
98
99 case CTRL_CLK_VIN_ID_GPC3:
100 data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
101 break;
102
103 case CTRL_CLK_VIN_ID_GPC4:
104 data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
105 break;
106
107 case CTRL_CLK_VIN_ID_GPC5:
108 data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
109 break;
110
111 case CTRL_CLK_VIN_ID_SYS:
112 case CTRL_CLK_VIN_ID_XBAR:
113 case CTRL_CLK_VIN_ID_LTC:
114 data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
115 break;
116
117 case CTRL_CLK_VIN_ID_SRAM:
118 data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
119 break;
120
121 default:
122 return -EINVAL;
123 }
124 if (data == 0xFFFFFFFF)
125 return -EINVAL;
126
127 gpc0interceptdata = (fuse_vin_cal_gpc0_icpt_int_data_v(gpc0data) <<
128 fuse_vin_cal_gpc0_icpt_frac_data_s()) +
129 fuse_vin_cal_gpc0_icpt_frac_data_v(gpc0data);
130 gpc0interceptdata = (gpc0interceptdata * 1000U) >>
131 fuse_vin_cal_gpc0_icpt_frac_data_s();
132
133 switch (vin_id) {
134 case CTRL_CLK_VIN_ID_GPC0:
135 break;
136
137 case CTRL_CLK_VIN_ID_GPC1:
138 case CTRL_CLK_VIN_ID_GPC2:
139 case CTRL_CLK_VIN_ID_GPC3:
140 case CTRL_CLK_VIN_ID_GPC4:
141 case CTRL_CLK_VIN_ID_GPC5:
142 case CTRL_CLK_VIN_ID_SYS:
143 case CTRL_CLK_VIN_ID_XBAR:
144 case CTRL_CLK_VIN_ID_LTC:
145 interceptdata = (fuse_vin_cal_gpc1_delta_icpt_int_data_v(data) <<
146 fuse_vin_cal_gpc1_delta_icpt_frac_data_s()) +
147 fuse_vin_cal_gpc1_delta_icpt_frac_data_v(data);
148 interceptdata = (interceptdata * 1000U) >>
149 fuse_vin_cal_gpc1_delta_icpt_frac_data_s();
150 break;
151
152 case CTRL_CLK_VIN_ID_SRAM:
153 interceptdata = (fuse_vin_cal_sram_delta_icpt_int_data_v(data) <<
154 fuse_vin_cal_sram_delta_icpt_frac_data_s()) +
155 fuse_vin_cal_sram_delta_icpt_frac_data_v(data);
156 interceptdata = (interceptdata * 1000U) >>
157 fuse_vin_cal_sram_delta_icpt_frac_data_s();
158 break;
159
160 default:
161 return -EINVAL;
162 }
163
164 if (fuse_vin_cal_gpc1_delta_icpt_sign_data_v(data))
165 *intercept = gpc0interceptdata - interceptdata;
166 else
167 *intercept = gpc0interceptdata + interceptdata;
168
169 /* slope */
170 gpc0slopedata = (fuse_vin_cal_gpc0_slope_int_data_v(gpc0data) <<
171 fuse_vin_cal_gpc0_slope_frac_data_s()) +
172 fuse_vin_cal_gpc0_slope_frac_data_v(gpc0data);
173 gpc0slopedata = (gpc0slopedata * 1000U) >>
174 fuse_vin_cal_gpc0_slope_frac_data_s();
175 switch (vin_id) {
176 case CTRL_CLK_VIN_ID_GPC0:
177 break;
178
179 case CTRL_CLK_VIN_ID_GPC1:
180 case CTRL_CLK_VIN_ID_GPC2:
181 case CTRL_CLK_VIN_ID_GPC3:
182 case CTRL_CLK_VIN_ID_GPC4:
183 case CTRL_CLK_VIN_ID_GPC5:
184 case CTRL_CLK_VIN_ID_SYS:
185 case CTRL_CLK_VIN_ID_XBAR:
186 case CTRL_CLK_VIN_ID_LTC:
187 case CTRL_CLK_VIN_ID_SRAM:
188 slopedata =
189 (fuse_vin_cal_gpc1_delta_slope_int_data_v(data)) * 1000;
190 break;
191
192 default:
193 return -EINVAL;
194 }
195
196 if (fuse_vin_cal_gpc1_delta_slope_sign_data_v(data))
197 *slope = gpc0slopedata - slopedata;
198 else
199 *slope = gpc0slopedata + slopedata;
200 return 0;
201}
202
203static u32 read_vin_cal_gain_offset_fuse(struct gk20a *g,
204 u32 vin_id, s8 *gain,
205 s8 *offset)
206{
207 u32 data = 0;
208
209 switch (vin_id) {
210 case CTRL_CLK_VIN_ID_GPC0:
211 data = gk20a_readl(g, fuse_vin_cal_gpc0_r());
212 break;
213
214 case CTRL_CLK_VIN_ID_GPC1:
215 data = gk20a_readl(g, fuse_vin_cal_gpc1_delta_r());
216 break;
217
218 case CTRL_CLK_VIN_ID_GPC2:
219 data = gk20a_readl(g, fuse_vin_cal_gpc2_delta_r());
220 break;
221
222 case CTRL_CLK_VIN_ID_GPC3:
223 data = gk20a_readl(g, fuse_vin_cal_gpc3_delta_r());
224 break;
225
226 case CTRL_CLK_VIN_ID_GPC4:
227 data = gk20a_readl(g, fuse_vin_cal_gpc4_delta_r());
228 break;
229
230 case CTRL_CLK_VIN_ID_GPC5:
231 data = gk20a_readl(g, fuse_vin_cal_gpc5_delta_r());
232 break;
233
234 case CTRL_CLK_VIN_ID_SYS:
235 case CTRL_CLK_VIN_ID_XBAR:
236 case CTRL_CLK_VIN_ID_LTC:
237 data = gk20a_readl(g, fuse_vin_cal_shared_delta_r());
238 break;
239
240 case CTRL_CLK_VIN_ID_SRAM:
241 data = gk20a_readl(g, fuse_vin_cal_sram_delta_r());
242 break;
243
244 default:
245 return -EINVAL;
246 }
247 if (data == 0xFFFFFFFF)
248 return -EINVAL;
249 *gain = (s8) (data >> 16) & 0x1f;
250 *offset = (s8) data & 0x7f;
251
252 return 0;
253}
254
255u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g, 63u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
256 struct avfsvinobjs *pvinobjs, 64 struct avfsvinobjs *pvinobjs,
257 struct vin_device_v20 *pvindev) 65 struct vin_device_v20 *pvindev)
@@ -260,13 +68,13 @@ u32 clk_avfs_get_vin_cal_fuse_v10(struct gk20a *g,
260 u32 slope, intercept; 68 u32 slope, intercept;
261 u8 i; 69 u8 i;
262 70
263 if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) { 71 if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
264 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), 72 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
265 struct vin_device_v20 *, pvindev, i) { 73 struct vin_device_v20 *, pvindev, i) {
266 slope = 0; 74 slope = 0;
267 intercept = 0; 75 intercept = 0;
268 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); 76 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
269 status = read_vin_cal_slope_intercept_fuse(g, 77 status = g->ops.fuse.read_vin_cal_slope_intercept_fuse(g,
270 pvindev->super.id, &slope, &intercept); 78 pvindev->super.id, &slope, &intercept);
271 if (status) { 79 if (status) {
272 nvgpu_err(g, 80 nvgpu_err(g,
@@ -291,13 +99,13 @@ u32 clk_avfs_get_vin_cal_fuse_v20(struct gk20a *g,
291 s8 gain, offset; 99 s8 gain, offset;
292 u8 i; 100 u8 i;
293 101
294 if (pvinobjs->calibration_rev_vbios == read_vin_cal_fuse_rev(g)) { 102 if (pvinobjs->calibration_rev_vbios == g->ops.fuse.read_vin_cal_fuse_rev(g)) {
295 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super), 103 BOARDOBJGRP_FOR_EACH(&(pvinobjs->super.super),
296 struct vin_device_v20 *, pvindev, i) { 104 struct vin_device_v20 *, pvindev, i) {
297 gain = 0; 105 gain = 0;
298 offset = 0; 106 offset = 0;
299 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i); 107 pvindev = (struct vin_device_v20 *)CLK_GET_VIN_DEVICE(pvinobjs, i);
300 status = read_vin_cal_gain_offset_fuse(g, 108 status = g->ops.fuse.read_vin_cal_gain_offset_fuse(g,
301 pvindev->super.id, &gain, &offset); 109 pvindev->super.id, &gain, &offset);
302 if (status) { 110 if (status) {
303 nvgpu_err(g, 111 nvgpu_err(g,
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:43:59 -0400