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authorPhilip Elcan <pelcan@nvidia.com>2018-08-27 12:45:27 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-10 18:23:45 -0400
commitd2be65315a9ebfc88e77489571a31c48b3d21284 (patch)
treeff4a2d2d90ad1b6f3768bcb8e67176202ccfe97c /drivers/gpu/nvgpu/clk/clk_mclk.h
parentc86f185d1022de18a1a1073aa91d2b06aa59e2fc (diff)
gpu: nvgpu: fix some MISRA 10.3 violations
Fix MISRA 10.3 violations in mclk_gp106.c. Cleanup cases where values were being assigned to narrower types. Changes in mclk_gp106.c required updates to other files to resolve errors and prevent introducing new violations. JIRA NVGPU-647 Change-Id: Ifdb03ad41d9dbf05dbcf79494ae8565fff6ee083 Signed-off-by: Philip Elcan <pelcan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809366 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_mclk.h')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_mclk.h10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h
index a0d3fd5d..00356c98 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.h
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.h
@@ -1,5 +1,5 @@
1/* 1/*
2* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. 2* Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
3* 3*
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,10 +25,10 @@
25 25
26#include <nvgpu/lock.h> 26#include <nvgpu/lock.h>
27 27
28#define GP106_MCLK_LOW_SPEED 0 28#define GP106_MCLK_LOW_SPEED 0U
29#define GP106_MCLK_MID_SPEED 1 29#define GP106_MCLK_MID_SPEED 1U
30#define GP106_MCLK_HIGH_SPEED 2 30#define GP106_MCLK_HIGH_SPEED 2U
31#define GP106_MCLK_NUM_SPEED 3 31#define GP106_MCLK_NUM_SPEED 3U
32 32
33enum gk20a_mclk_speed { 33enum gk20a_mclk_speed {
34 gk20a_mclk_low_speed, 34 gk20a_mclk_low_speed,