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authorDavid Nieto <dmartineznie@nvidia.com>2016-10-07 19:25:04 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:52 -0500
commitc4bb19d46e1c9121a0948fa506098cbf2f64e2a6 (patch)
tree29647922e8374377c05ab976c7616410d85eda4d /drivers/gpu/nvgpu/clk/clk_mclk.h
parentbfc12d25a41c2b5a4d06f233f16331e43c489d8e (diff)
nvgpu: gpu: arbiter for vf switch management
JIRA DNVGPU-143 The arbiter is charged with selecting the proper frequencies when multiple applications submit simultaneously clock change requests On the current implementation, the arbiter guarantees that the selected frequency will be always higher or equal to the request, as long as the request is in range. The current code is not yet realtime friendly, as requests are not pre-allocated. Summary of changes: (1) pstate/vf switch no longer selects boot frequency (2) changed mclk code change to accept input freq (3) added arbiter (4) now a single session can submit concurrent requests the last request is the one that applies for that session (5) modified locking mechanism to reduce lock contention (6) Added callback to notify the arbiter that the VF table has changed and is no longer valid (PMU/Thermals must call this when VF table is invalid) (7) changed internal API to work with MHz (8) added debugfs for stats Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63 Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1239461 Reviewed-by: Thomas Fleury <tfleury@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1267120 Reviewed-by: Automatic_Commit_Validation_User
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_mclk.h')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_mclk.h10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h
index 9d193c96..e3e6c1ee 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.h
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.h
@@ -22,9 +22,12 @@ enum gk20a_mclk_speed {
22 gk20a_mclk_high_speed, 22 gk20a_mclk_high_speed,
23}; 23};
24 24
25#define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed
26#define MCLK_LOW_SPEED_LIMIT 405 25#define MCLK_LOW_SPEED_LIMIT 405
27#define MCLK_MID_SPEED_LIMIT 810 26#define MCLK_MID_SPEED_LIMIT 810
27#define MCLK_HIGH_SPEED_LIMIT 3003
28
29#define DEFAULT_BOOT_MCLK_SPEED MCLK_HIGH_SPEED_LIMIT
30
28struct clk_mclk_state { 31struct clk_mclk_state {
29 enum gk20a_mclk_speed speed; 32 enum gk20a_mclk_speed speed;
30 struct mutex mclk_mutex; 33 struct mutex mclk_mutex;
@@ -32,7 +35,7 @@ struct clk_mclk_state {
32 bool init; 35 bool init;
33 36
34 /* function pointers */ 37 /* function pointers */
35 int (*change)(struct gk20a *g, enum gk20a_mclk_speed speed); 38 int (*change)(struct gk20a *g, u16 val);
36 39
37#ifdef CONFIG_DEBUG_FS 40#ifdef CONFIG_DEBUG_FS
38 s64 switch_max; 41 s64 switch_max;
@@ -45,7 +48,6 @@ struct clk_mclk_state {
45}; 48};
46 49
47int clk_mclkseq_init_mclk_gddr5(struct gk20a *g); 50int clk_mclkseq_init_mclk_gddr5(struct gk20a *g);
48int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, 51int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val);
49 enum gk20a_mclk_speed speed);
50 52
51#endif 53#endif