gpu: nvgpu: mclk switching sequences for PG419

VBIOS memory settings have been updated for PG419, significantly
modifying MCLK switching sequences. This change adds support for
PG419 tables, while remaining backward compatible with PG418.

Bug 1921082
JIRA EVLR-1269

Change-Id: Ia8a1f8b3f482e348a46f0acb540af23287d9c11e
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: http://git-master/r/1484110
(cherry picked from commit c2444ae89caf97da2702e8486cc8fb162b4f50b1)
Reviewed-on: http://git-master/r/1485300
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 9 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h
index 64eee5ac..4918b917 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.h
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.h
@@ -16,6 +16,14 @@
 
 #include <nvgpu/lock.h>
 
+#define GP106_MCLK_LOW_SPEED    0
+#define GP106_MCLK_MID_SPEED    1
+#define GP106_MCLK_HIGH_SPEED   2
+#define GP106_MCLK_NUM_SPEED    3
+
+#define GP106_MEM_CONFIG_GDDR5_PG418    0
+#define GP106_MEM_CONFIG_GDDR5_PG419    1
+
 enum gk20a_mclk_speed {
         gk20a_mclk_low_speed,
         gk20a_mclk_mid_speed,
@@ -23,7 +31,7 @@ enum gk20a_mclk_speed {
 };
 
 struct clk_mclk_state {
-        enum gk20a_mclk_speed speed;
+        u32 speed;
         struct nvgpu_mutex mclk_lock;
         struct nvgpu_mutex data_lock;
 
@@ -33,9 +41,6 @@ struct clk_mclk_state {
         void *vreg_buf;
         bool init;
 
-        /* function pointers */
-        int (*change)(struct gk20a *g, u16 val);
-
 #ifdef CONFIG_DEBUG_FS
         s64 switch_max;
         s64 switch_min;