gpu: nvgpu: construct/load tabels & set voltage

- Read voltage tables from VBIOS & construct
  then send to PMU.
- compare & set voltage based on
  mclk/gpc2clk clk, take higher voltage
  between two & set.

JIRA DNVGPU-122

Change-Id: I23e7b101a3b1c1b6596620fc6b8319c70bd9a488
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1224365
(cherry picked from commit e0055c3ec798b8312df3fa9bf92bde8c57c6f58c)
Reviewed-on: http://git-master/r/1244657
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 1 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c
index b63fab1e..7b15767b 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.c
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.c
@@ -23,10 +23,6 @@
 
 #define VREG_COUNT 24
 
-#define DEFAULT_BOOT_MCLK_SPEED gk20a_mclk_high_speed
-#define MCLK_LOW_SPEED_LIMIT 405
-#define MCLK_MID_SPEED_LIMIT 810
-
 struct memory_link_training_pattern {
         u32 regaddr;
         u32 writeval;
@@ -2220,7 +2216,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g)
 
         mclk->init = true;
 
-        return mclk->change(g, DEFAULT_BOOT_MCLK_SPEED);
+        return 0;
 }
 
 int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, enum gk20a_mclk_speed speed)