diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-04-06 15:17:26 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-07 16:48:24 -0400 |
commit | 1add126551309a323ae422be41c9db2203bbe112 (patch) | |
tree | d9a620ca88a3c73c0f3dc0f7079ea4d3c24eb075 /drivers/gpu/nvgpu/clk/clk_mclk.c | |
parent | 86ecddf68734e4a938eda351f4dde11ab507de3f (diff) |
gpu: nvgpu: clk: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer,
which is not portable across operating systems. The new nvgpu_err()
and nvgpu_warn() macros take struct gk20a pointer. Convert code
to use the more portable macros.
JIRA NVGPU-16
Change-Id: I58bb9e2fb7e5b18f74fbb92b70150cce97968fc3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1457347
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_mclk.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_mclk.c | 21 |
1 files changed, 8 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c index f973a696..690f8681 100644 --- a/drivers/gpu/nvgpu/clk/clk_mclk.c +++ b/drivers/gpu/nvgpu/clk/clk_mclk.c | |||
@@ -1979,7 +1979,7 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg, | |||
1979 | gk20a_dbg_info(""); | 1979 | gk20a_dbg_info(""); |
1980 | 1980 | ||
1981 | if (status != 0) { | 1981 | if (status != 0) { |
1982 | gk20a_err(dev_from_gk20a(g), "mclk seq_script cmd aborted"); | 1982 | nvgpu_err(g, "mclk seq_script cmd aborted"); |
1983 | msg_status = -ENOENT; | 1983 | msg_status = -ENOENT; |
1984 | goto status_update; | 1984 | goto status_update; |
1985 | } | 1985 | } |
@@ -2088,8 +2088,7 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
2088 | } | 2088 | } |
2089 | 2089 | ||
2090 | if (shadow_idx > fb_fbpa_fbio_delay_priv_max_v()) { | 2090 | if (shadow_idx > fb_fbpa_fbio_delay_priv_max_v()) { |
2091 | gk20a_err(dev_from_gk20a(g), | 2091 | nvgpu_err(g, "invalid shadow reg script index"); |
2092 | "invalid shadow reg script index"); | ||
2093 | status = -EINVAL; | 2092 | status = -EINVAL; |
2094 | goto done; | 2093 | goto done; |
2095 | } | 2094 | } |
@@ -2140,8 +2139,8 @@ static int mclk_get_memclk_table(struct gk20a *g) | |||
2140 | } | 2139 | } |
2141 | 2140 | ||
2142 | if (cmd_idx > fb_fbpa_fbio_cmd_delay_cmd_priv_max_v()) { | 2141 | if (cmd_idx > fb_fbpa_fbio_cmd_delay_cmd_priv_max_v()) { |
2143 | gk20a_err(dev_from_gk20a(g), | 2142 | nvgpu_err(g, |
2144 | "invalid shadow reg cmd script index"); | 2143 | "invalid shadow reg cmd script index"); |
2145 | status = -EINVAL; | 2144 | status = -EINVAL; |
2146 | goto done; | 2145 | goto done; |
2147 | } | 2146 | } |
@@ -2236,8 +2235,7 @@ int clk_mclkseq_init_mclk_gddr5(struct gk20a *g) | |||
2236 | 2235 | ||
2237 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); | 2236 | mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32)); |
2238 | if (!mclk->vreg_buf) { | 2237 | if (!mclk->vreg_buf) { |
2239 | gk20a_err(dev_from_gk20a(g), | 2238 | nvgpu_err(g, "unable to allocate memory for VREG"); |
2240 | "unable to allocate memory for VREG"); | ||
2241 | err = -ENOMEM; | 2239 | err = -ENOMEM; |
2242 | goto fail_data_mutex; | 2240 | goto fail_data_mutex; |
2243 | } | 2241 | } |
@@ -2318,8 +2316,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2318 | } | 2316 | } |
2319 | break; | 2317 | break; |
2320 | default: | 2318 | default: |
2321 | gk20a_err(dev_from_gk20a(g), | 2319 | nvgpu_err(g, "Illegal MCLK clock change"); |
2322 | "Illegal MCLK clock change"); | ||
2323 | status = -EINVAL; | 2320 | status = -EINVAL; |
2324 | goto exit_status; | 2321 | goto exit_status; |
2325 | } | 2322 | } |
@@ -2368,8 +2365,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2368 | mclk_seq_pmucmdhandler, | 2365 | mclk_seq_pmucmdhandler, |
2369 | &seq_completion_status, &seqdesc, ~0); | 2366 | &seq_completion_status, &seqdesc, ~0); |
2370 | if (status) { | 2367 | if (status) { |
2371 | gk20a_err(dev_from_gk20a(g), | 2368 | nvgpu_err(g, "unable to post seq script exec cmd for unit %x", |
2372 | "unable to post seq script exec cmd for unit %x ", | ||
2373 | cmd.hdr.unit_id); | 2369 | cmd.hdr.unit_id); |
2374 | goto exit_status; | 2370 | goto exit_status; |
2375 | } | 2371 | } |
@@ -2377,8 +2373,7 @@ int clk_mclkseq_change_mclk_gddr5(struct gk20a *g, u16 val) | |||
2377 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), | 2373 | pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)), |
2378 | &seq_completion_status, 0); | 2374 | &seq_completion_status, 0); |
2379 | if (seq_completion_status != 0) { | 2375 | if (seq_completion_status != 0) { |
2380 | gk20a_err(dev_from_gk20a(g), | 2376 | nvgpu_err(g, "seq_script update failed"); |
2381 | "seq_script update failed"); | ||
2382 | status = -EBUSY; | 2377 | status = -EBUSY; |
2383 | goto exit_status; | 2378 | goto exit_status; |
2384 | } | 2379 | } |