summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/clk/clk_freq_controller.h
diff options
context:
space:
mode:
authorsmadhavan <smadhavan@nvidia.com>2018-09-11 02:36:17 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-14 02:45:22 -0400
commita605a09e2a74f31abc3755a6e383311317e3b909 (patch)
tree553a802073c55e7bd51f7ac7ecf984008bffe480 /drivers/gpu/nvgpu/clk/clk_freq_controller.h
parent852d77ffafdb8726a8e3cb1cc45cb63b90cb4c3c (diff)
nvgpu: clk: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in clk by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I5305066dffcfb03e3c99fb501e783dcc70765b11 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1809069 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: Adeel Raza <araza@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.h')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_freq_controller.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.h b/drivers/gpu/nvgpu/clk/clk_freq_controller.h
index 659b75d5..7ae475c1 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.h
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.h
@@ -20,8 +20,8 @@
20 * DEALINGS IN THE SOFTWARE. 20 * DEALINGS IN THE SOFTWARE.
21*/ 21*/
22 22
23#ifndef _CLK_FREQ_CONTROLLER_H_ 23#ifndef NVGPU_CLK_FREQ_CONTROLLER_H
24#define _CLK_FREQ_CONTROLLER_H_ 24#define NVGPU_CLK_FREQ_CONTROLLER_H
25 25
26#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFF 26#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL 0xFF
27#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00 27#define CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS 0x00
@@ -81,4 +81,4 @@ struct clk_freq_controllers {
81int clk_freq_controller_sw_setup(struct gk20a *g); 81int clk_freq_controller_sw_setup(struct gk20a *g);
82int clk_freq_controller_pmu_setup(struct gk20a *g); 82int clk_freq_controller_pmu_setup(struct gk20a *g);
83 83
84#endif 84#endif /* NVGPU_CLK_FREQ_CONTROLLER_H */