diff options
author | Srirangan <smadhavan@nvidia.com> | 2018-09-04 06:46:20 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-05 23:38:33 -0400 |
commit | ef851272e5201f343c9b287a9eacfc25d4912276 (patch) | |
tree | 2c7f85f168258e8b8779dd3ef32f1b18621fa6a7 /drivers/gpu/nvgpu/clk/clk_freq_controller.c | |
parent | 78b4ab269f5d733c8b540a6a75db1f390172cc29 (diff) |
gpu: nvgpu: clk: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: I228f04adea809e1dd4e6826bf1a04f051a533102
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796831
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 30 |
1 files changed, 20 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index 9091f71b..aa2a3a54 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -41,8 +41,9 @@ static u32 clk_freq_controller_pmudatainit_super(struct gk20a *g, | |||
41 | u32 status = 0; | 41 | u32 status = 0; |
42 | 42 | ||
43 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 43 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
44 | if (status) | 44 | if (status) { |
45 | return status; | 45 | return status; |
46 | } | ||
46 | 47 | ||
47 | pfreq_cntlr_set = | 48 | pfreq_cntlr_set = |
48 | (struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata; | 49 | (struct nv_pmu_clk_clk_freq_controller_boardobj_set *)ppmudata; |
@@ -73,8 +74,9 @@ static u32 clk_freq_controller_pmudatainit_pi(struct gk20a *g, | |||
73 | 74 | ||
74 | status = clk_freq_controller_pmudatainit_super(g, | 75 | status = clk_freq_controller_pmudatainit_super(g, |
75 | board_obj_ptr, ppmudata); | 76 | board_obj_ptr, ppmudata); |
76 | if (status) | 77 | if (status) { |
77 | return -1; | 78 | return -1; |
79 | } | ||
78 | 80 | ||
79 | pfreq_cntlr_pi_set = | 81 | pfreq_cntlr_pi_set = |
80 | (struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *) | 82 | (struct nv_pmu_clk_clk_freq_controller_pi_boardobj_set *) |
@@ -101,8 +103,9 @@ static u32 clk_freq_controller_construct_super(struct gk20a *g, | |||
101 | u32 status = 0; | 103 | u32 status = 0; |
102 | 104 | ||
103 | status = boardobj_construct_super(g, ppboardobj, size, pargs); | 105 | status = boardobj_construct_super(g, ppboardobj, size, pargs); |
104 | if (status) | 106 | if (status) { |
105 | return -EINVAL; | 107 | return -EINVAL; |
108 | } | ||
106 | 109 | ||
107 | pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs; | 110 | pfreq_cntlr_tmp = (struct clk_freq_controller *)pargs; |
108 | pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj; | 111 | pfreq_cntlr = (struct clk_freq_controller *)*ppboardobj; |
@@ -132,8 +135,9 @@ static u32 clk_freq_controller_construct_pi(struct gk20a *g, | |||
132 | 135 | ||
133 | status = clk_freq_controller_construct_super(g, ppboardobj, | 136 | status = clk_freq_controller_construct_super(g, ppboardobj, |
134 | size, pargs); | 137 | size, pargs); |
135 | if (status) | 138 | if (status) { |
136 | return -EINVAL; | 139 | return -EINVAL; |
140 | } | ||
137 | 141 | ||
138 | pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj; | 142 | pfreq_cntlr_pi = (struct clk_freq_controller_pi *)*ppboardobj; |
139 | pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs; | 143 | pfreq_cntlr_pi_tmp = (struct clk_freq_controller_pi *)pargs; |
@@ -159,13 +163,15 @@ static struct clk_freq_controller *clk_clk_freq_controller_construct( | |||
159 | struct boardobj *board_obj_ptr = NULL; | 163 | struct boardobj *board_obj_ptr = NULL; |
160 | u32 status = 0; | 164 | u32 status = 0; |
161 | 165 | ||
162 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI) | 166 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_FREQ_CONTROLLER_TYPE_PI) { |
163 | return NULL; | 167 | return NULL; |
168 | } | ||
164 | 169 | ||
165 | status = clk_freq_controller_construct_pi(g, &board_obj_ptr, | 170 | status = clk_freq_controller_construct_pi(g, &board_obj_ptr, |
166 | sizeof(struct clk_freq_controller_pi), pargs); | 171 | sizeof(struct clk_freq_controller_pi), pargs); |
167 | if (status) | 172 | if (status) { |
168 | return NULL; | 173 | return NULL; |
174 | } | ||
169 | 175 | ||
170 | return (struct clk_freq_controller *)board_obj_ptr; | 176 | return (struct clk_freq_controller *)board_obj_ptr; |
171 | } | 177 | } |
@@ -222,8 +228,9 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
222 | sizeof(struct vbios_fct_1x_entry)); | 228 | sizeof(struct vbios_fct_1x_entry)); |
223 | 229 | ||
224 | if (!BIOS_GET_FIELD(entry.flags0, | 230 | if (!BIOS_GET_FIELD(entry.flags0, |
225 | NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) | 231 | NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE)) { |
226 | continue; | 232 | continue; |
233 | } | ||
227 | 234 | ||
228 | freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD( | 235 | freq_controller_data.board_obj.type = (u8)BIOS_GET_FIELD( |
229 | entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE); | 236 | entry.flags0, NV_VBIOS_FCT_1X_ENTRY_FLAGS0_TYPE); |
@@ -286,8 +293,9 @@ static u32 clk_get_freq_controller_table(struct gk20a *g, | |||
286 | NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG); | 293 | NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG); |
287 | 294 | ||
288 | if (ptmp_freq_cntr_pi->volt_delta_max < | 295 | if (ptmp_freq_cntr_pi->volt_delta_max < |
289 | ptmp_freq_cntr_pi->volt_delta_min) | 296 | ptmp_freq_cntr_pi->volt_delta_min) { |
290 | goto done; | 297 | goto done; |
298 | } | ||
291 | 299 | ||
292 | pclk_freq_cntr = clk_clk_freq_controller_construct(g, | 300 | pclk_freq_cntr = clk_clk_freq_controller_construct(g, |
293 | (void *)&freq_controller_data); | 301 | (void *)&freq_controller_data); |
@@ -325,8 +333,9 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
325 | 333 | ||
326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; | 334 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; |
327 | 335 | ||
328 | if (!pboardobjgrp->bconstructed) | 336 | if (!pboardobjgrp->bconstructed) { |
329 | return -EINVAL; | 337 | return -EINVAL; |
338 | } | ||
330 | 339 | ||
331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 340 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
332 | 341 | ||
@@ -347,8 +356,9 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
347 | 356 | ||
348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 357 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
349 | if (((u32)BIT(idx) & | 358 | if (((u32)BIT(idx) & |
350 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 359 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
351 | return -EINVAL; | 360 | return -EINVAL; |
361 | } | ||
352 | 362 | ||
353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 363 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
354 | &pgrp_set->objects[idx].data.board_obj; | 364 | &pgrp_set->objects[idx].data.board_obj; |