diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2018-04-18 22:39:46 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-09 21:26:04 -0400 |
commit | dd739fcb039d51606e9a5454ec0aab17bcb01965 (patch) | |
tree | 806ba8575d146367ad1be00086ca0cdae35a6b28 /drivers/gpu/nvgpu/clk/clk_freq_controller.c | |
parent | 7e66f2a63d4855e763fa768047dfc32f6f96b771 (diff) |
gpu: nvgpu: Remove gk20a_dbg* functions
Switch all logging to nvgpu_log*(). gk20a_dbg* macros are
intentionally left there because of use from other repositories.
Because the new functions do not work without a pointer to struct
gk20a, and piping it just for logging is excessive, some log messages
are deleted.
Change-Id: I00e22e75fe4596a330bb0282ab4774b3639ee31e
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704148
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_freq_controller.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_freq_controller.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c index fce177a7..9091f71b 100644 --- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c +++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -321,7 +321,7 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
321 | u32 status; | 321 | u32 status; |
322 | struct boardobjgrp *pboardobjgrp = NULL; | 322 | struct boardobjgrp *pboardobjgrp = NULL; |
323 | 323 | ||
324 | gk20a_dbg_info(""); | 324 | nvgpu_log_info(g, " "); |
325 | 325 | ||
326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; | 326 | pboardobjgrp = &g->clk_pmu.clk_freq_controllers.super.super; |
327 | 327 | ||
@@ -330,7 +330,7 @@ u32 clk_freq_controller_pmu_setup(struct gk20a *g) | |||
330 | 330 | ||
331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 331 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
332 | 332 | ||
333 | gk20a_dbg_info("Done"); | 333 | nvgpu_log_info(g, "Done"); |
334 | return status; | 334 | return status; |
335 | } | 335 | } |
336 | 336 | ||
@@ -343,7 +343,7 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
343 | (struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *) | 343 | (struct nv_pmu_clk_clk_freq_controller_boardobj_grp_set *) |
344 | pmuboardobjgrp; | 344 | pmuboardobjgrp; |
345 | 345 | ||
346 | gk20a_dbg_info(""); | 346 | nvgpu_log_info(g, " "); |
347 | 347 | ||
348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 348 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
349 | if (((u32)BIT(idx) & | 349 | if (((u32)BIT(idx) & |
@@ -352,7 +352,7 @@ static u32 _clk_freq_controller_devgrp_pmudata_instget(struct gk20a *g, | |||
352 | 352 | ||
353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 353 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
354 | &pgrp_set->objects[idx].data.board_obj; | 354 | &pgrp_set->objects[idx].data.board_obj; |
355 | gk20a_dbg_info(" Done"); | 355 | nvgpu_log_info(g, " Done"); |
356 | return 0; | 356 | return 0; |
357 | } | 357 | } |
358 | 358 | ||
@@ -392,7 +392,7 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
392 | u8 i; | 392 | u8 i; |
393 | u8 j; | 393 | u8 j; |
394 | 394 | ||
395 | gk20a_dbg_info(""); | 395 | nvgpu_log_info(g, " "); |
396 | 396 | ||
397 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; | 397 | pclk_freq_controllers = &g->clk_pmu.clk_freq_controllers; |
398 | status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); | 398 | status = boardobjgrpconstruct_e32(g, &pclk_freq_controllers->super); |
@@ -447,6 +447,6 @@ u32 clk_freq_controller_sw_setup(struct gk20a *g) | |||
447 | freq_ctrl_load_mask.super, i); | 447 | freq_ctrl_load_mask.super, i); |
448 | } | 448 | } |
449 | done: | 449 | done: |
450 | gk20a_dbg_info(" done status %x", status); | 450 | nvgpu_log_info(g, " done status %x", status); |
451 | return status; | 451 | return status; |
452 | } | 452 | } |