gpu: nvgpu: Update clk_fll interface as per chips_a

Two new members added to fll struct and code modified to support
GV100 VBIOS NAFLL tables
Add g->ops for getting vbios clk domains

JIRA NVGPUGV100-39

Change-Id: Iaabea893d55d44a272e2bce2b1d525b122cd36f5
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594289
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Tested-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_fll.h b/drivers/gpu/nvgpu/clk/clk_fll.h
index 481ca707..79ecf5e1 100644
--- a/drivers/gpu/nvgpu/clk/clk_fll.h
+++ b/drivers/gpu/nvgpu/clk/clk_fll.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -61,10 +61,15 @@ struct fll_device {
         u8 min_freq_vfe_idx;
         u8 freq_ctrl_idx;
         u8 target_regime_id_override;
+        bool b_skip_pldiv_below_dvco_min;
+        bool b_dvco_1x;
         struct boardobjgrpmask_e32 lut_prog_broadcast_slave_mask;
         fll_lut_broadcast_slave_register *lut_broadcast_slave_register;
 };
 
+u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain);
+u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain);
+
 #define CLK_FLL_LUT_VF_NUM_ENTRIES(pclk) \
         (pclk->avfs_fllobjs.lut_num_entries)