diff options
author | Srirangan <smadhavan@nvidia.com> | 2018-09-04 06:46:20 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-05 23:38:33 -0400 |
commit | ef851272e5201f343c9b287a9eacfc25d4912276 (patch) | |
tree | 2c7f85f168258e8b8779dd3ef32f1b18621fa6a7 /drivers/gpu/nvgpu/clk/clk_fll.c | |
parent | 78b4ab269f5d733c8b540a6a75db1f390172cc29 (diff) |
gpu: nvgpu: clk: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: I228f04adea809e1dd4e6826bf1a04f051a533102
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796831
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_fll.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_fll.c | 63 |
1 files changed, 39 insertions, 24 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c index a05fdf22..0fd9c33f 100644 --- a/drivers/gpu/nvgpu/clk/clk_fll.c +++ b/drivers/gpu/nvgpu/clk/clk_fll.c | |||
@@ -84,8 +84,9 @@ static u32 _clk_fll_devgrp_pmudata_instget(struct gk20a *g, | |||
84 | 84 | ||
85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 85 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
86 | if (((u32)BIT(idx) & | 86 | if (((u32)BIT(idx) & |
87 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 87 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
88 | return -EINVAL; | 88 | return -EINVAL; |
89 | } | ||
89 | 90 | ||
90 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 91 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
91 | &pgrp_set->objects[idx].data.board_obj; | 92 | &pgrp_set->objects[idx].data.board_obj; |
@@ -104,8 +105,9 @@ static u32 _clk_fll_devgrp_pmustatus_instget(struct gk20a *g, | |||
104 | 105 | ||
105 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 106 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
106 | if (((u32)BIT(idx) & | 107 | if (((u32)BIT(idx) & |
107 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) | 108 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { |
108 | return -EINVAL; | 109 | return -EINVAL; |
110 | } | ||
109 | 111 | ||
110 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) | 112 | *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *) |
111 | &pgrp_get_status->objects[idx].data.board_obj; | 113 | &pgrp_get_status->objects[idx].data.board_obj; |
@@ -157,8 +159,9 @@ u32 clk_fll_sw_setup(struct gk20a *g) | |||
157 | boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL); | 159 | boardobjgrpmask_e32_init(&pfllobjs->lut_prog_master_mask, NULL); |
158 | 160 | ||
159 | status = devinit_get_fll_device_table(g, pfllobjs); | 161 | status = devinit_get_fll_device_table(g, pfllobjs); |
160 | if (status) | 162 | if (status) { |
161 | goto done; | 163 | goto done; |
164 | } | ||
162 | 165 | ||
163 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, | 166 | status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g, |
164 | &g->clk_pmu.avfs_fllobjs.super.super, | 167 | &g->clk_pmu.avfs_fllobjs.super.super, |
@@ -215,8 +218,9 @@ u32 clk_fll_pmu_setup(struct gk20a *g) | |||
215 | 218 | ||
216 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; | 219 | pboardobjgrp = &g->clk_pmu.avfs_fllobjs.super.super; |
217 | 220 | ||
218 | if (!pboardobjgrp->bconstructed) | 221 | if (!pboardobjgrp->bconstructed) { |
219 | return -EINVAL; | 222 | return -EINVAL; |
223 | } | ||
220 | 224 | ||
221 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 225 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
222 | 226 | ||
@@ -252,18 +256,20 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
252 | 256 | ||
253 | memcpy(&fll_desc_table_header_sz, fll_table_ptr, | 257 | memcpy(&fll_desc_table_header_sz, fll_table_ptr, |
254 | sizeof(struct fll_descriptor_header)); | 258 | sizeof(struct fll_descriptor_header)); |
255 | if (fll_desc_table_header_sz.size >= FLL_DESCRIPTOR_HEADER_10_SIZE_6) | 259 | if (fll_desc_table_header_sz.size >= FLL_DESCRIPTOR_HEADER_10_SIZE_6) { |
256 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_6; | 260 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_6; |
257 | else | 261 | } else { |
258 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_4; | 262 | desctablesize = FLL_DESCRIPTOR_HEADER_10_SIZE_4; |
263 | } | ||
259 | 264 | ||
260 | memcpy(&fll_desc_table_header, fll_table_ptr, desctablesize); | 265 | memcpy(&fll_desc_table_header, fll_table_ptr, desctablesize); |
261 | 266 | ||
262 | if (desctablesize == FLL_DESCRIPTOR_HEADER_10_SIZE_6) | 267 | if (desctablesize == FLL_DESCRIPTOR_HEADER_10_SIZE_6) { |
263 | pfllobjs->max_min_freq_mhz = | 268 | pfllobjs->max_min_freq_mhz = |
264 | fll_desc_table_header.max_min_freq_mhz; | 269 | fll_desc_table_header.max_min_freq_mhz; |
265 | else | 270 | } else { |
266 | pfllobjs->max_min_freq_mhz = 0; | 271 | pfllobjs->max_min_freq_mhz = 0; |
272 | } | ||
267 | 273 | ||
268 | /* Read table entries*/ | 274 | /* Read table entries*/ |
269 | fll_tbl_entry_ptr = fll_table_ptr + desctablesize; | 275 | fll_tbl_entry_ptr = fll_table_ptr + desctablesize; |
@@ -273,18 +279,20 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
273 | memcpy(&fll_desc_table_entry, fll_tbl_entry_ptr, | 279 | memcpy(&fll_desc_table_entry, fll_tbl_entry_ptr, |
274 | sizeof(struct fll_descriptor_entry_10)); | 280 | sizeof(struct fll_descriptor_entry_10)); |
275 | 281 | ||
276 | if (fll_desc_table_entry.fll_device_type == CTRL_CLK_FLL_TYPE_DISABLED) | 282 | if (fll_desc_table_entry.fll_device_type == CTRL_CLK_FLL_TYPE_DISABLED) { |
277 | continue; | 283 | continue; |
284 | } | ||
278 | 285 | ||
279 | fll_id = fll_desc_table_entry.fll_device_id; | 286 | fll_id = fll_desc_table_entry.fll_device_id; |
280 | 287 | ||
281 | if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { | 288 | if ( (u8)fll_desc_table_entry.vin_idx_logic != CTRL_CLK_VIN_ID_UNDEFINED) { |
282 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 289 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, |
283 | (u8)fll_desc_table_entry.vin_idx_logic); | 290 | (u8)fll_desc_table_entry.vin_idx_logic); |
284 | if (pvin_dev == NULL) | 291 | if (pvin_dev == NULL) { |
285 | return -EINVAL; | 292 | return -EINVAL; |
286 | else | 293 | } else { |
287 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 294 | pvin_dev->flls_shared_mask |= BIT(fll_id); |
295 | } | ||
288 | } else { | 296 | } else { |
289 | /* Return if Logic ADC device index is invalid*/ | 297 | /* Return if Logic ADC device index is invalid*/ |
290 | nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); | 298 | nvgpu_err(g, "Invalid Logic ADC specified for Nafll ID"); |
@@ -298,14 +306,16 @@ static u32 devinit_get_fll_device_table(struct gk20a *g, | |||
298 | if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { | 306 | if ( (u8)fll_desc_table_entry.vin_idx_sram != CTRL_CLK_VIN_ID_UNDEFINED) { |
299 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, | 307 | pvin_dev = CLK_GET_VIN_DEVICE(pvinobjs, |
300 | (u8)fll_desc_table_entry.vin_idx_sram); | 308 | (u8)fll_desc_table_entry.vin_idx_sram); |
301 | if (pvin_dev == NULL) | 309 | if (pvin_dev == NULL) { |
302 | return -EINVAL; | 310 | return -EINVAL; |
303 | else | 311 | } else { |
304 | pvin_dev->flls_shared_mask |= BIT(fll_id); | 312 | pvin_dev->flls_shared_mask |= BIT(fll_id); |
313 | } | ||
305 | } else { | 314 | } else { |
306 | /* Make sure VSELECT mode is set correctly to _LOGIC*/ | 315 | /* Make sure VSELECT mode is set correctly to _LOGIC*/ |
307 | if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) | 316 | if (fll_dev_data.lut_device.vselect_mode != CTRL_CLK_FLL_LUT_VSELECT_LOGIC) { |
308 | return -EINVAL; | 317 | return -EINVAL; |
318 | } | ||
309 | } | 319 | } |
310 | 320 | ||
311 | fll_dev_data.super.type = | 321 | fll_dev_data.super.type = |
@@ -357,25 +367,27 @@ done: | |||
357 | 367 | ||
358 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) | 368 | u32 nvgpu_clk_get_vbios_clk_domain_gv10x( u32 vbios_domain) |
359 | { | 369 | { |
360 | if (vbios_domain == 0) | 370 | if (vbios_domain == 0) { |
361 | return CTRL_CLK_DOMAIN_GPCCLK; | 371 | return CTRL_CLK_DOMAIN_GPCCLK; |
362 | else if (vbios_domain == 1) | 372 | } else if (vbios_domain == 1) { |
363 | return CTRL_CLK_DOMAIN_XBARCLK; | 373 | return CTRL_CLK_DOMAIN_XBARCLK; |
364 | else if (vbios_domain == 3) | 374 | } else if (vbios_domain == 3) { |
365 | return CTRL_CLK_DOMAIN_SYSCLK; | 375 | return CTRL_CLK_DOMAIN_SYSCLK; |
366 | else if (vbios_domain == 5) | 376 | } else if (vbios_domain == 5) { |
367 | return CTRL_CLK_DOMAIN_NVDCLK; | 377 | return CTRL_CLK_DOMAIN_NVDCLK; |
378 | } | ||
368 | return 0; | 379 | return 0; |
369 | } | 380 | } |
370 | 381 | ||
371 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) | 382 | u32 nvgpu_clk_get_vbios_clk_domain_gp10x( u32 vbios_domain) |
372 | { | 383 | { |
373 | if (vbios_domain == 0) | 384 | if (vbios_domain == 0) { |
374 | return CTRL_CLK_DOMAIN_GPC2CLK; | 385 | return CTRL_CLK_DOMAIN_GPC2CLK; |
375 | else if (vbios_domain == 1) | 386 | } else if (vbios_domain == 1) { |
376 | return CTRL_CLK_DOMAIN_XBAR2CLK; | 387 | return CTRL_CLK_DOMAIN_XBAR2CLK; |
377 | else if (vbios_domain == 3) | 388 | } else if (vbios_domain == 3) { |
378 | return CTRL_CLK_DOMAIN_SYS2CLK; | 389 | return CTRL_CLK_DOMAIN_SYS2CLK; |
390 | } | ||
379 | return 0; | 391 | return 0; |
380 | } | 392 | } |
381 | 393 | ||
@@ -384,8 +396,9 @@ static u32 lutbroadcastslaveregister(struct gk20a *g, | |||
384 | struct fll_device *pfll, | 396 | struct fll_device *pfll, |
385 | struct fll_device *pfll_slave) | 397 | struct fll_device *pfll_slave) |
386 | { | 398 | { |
387 | if (pfll->clk_domain != pfll_slave->clk_domain) | 399 | if (pfll->clk_domain != pfll_slave->clk_domain) { |
388 | return -EINVAL; | 400 | return -EINVAL; |
401 | } | ||
389 | 402 | ||
390 | return boardobjgrpmask_bitset(&pfll-> | 403 | return boardobjgrpmask_bitset(&pfll-> |
391 | lut_prog_broadcast_slave_mask.super, | 404 | lut_prog_broadcast_slave_mask.super, |
@@ -403,8 +416,9 @@ static struct fll_device *construct_fll_device(struct gk20a *g, | |||
403 | nvgpu_log_info(g, " "); | 416 | nvgpu_log_info(g, " "); |
404 | status = boardobj_construct_super(g, &board_obj_ptr, | 417 | status = boardobj_construct_super(g, &board_obj_ptr, |
405 | sizeof(struct fll_device), pargs); | 418 | sizeof(struct fll_device), pargs); |
406 | if (status) | 419 | if (status) { |
407 | return NULL; | 420 | return NULL; |
421 | } | ||
408 | 422 | ||
409 | pfll_dev = (struct fll_device *)pargs; | 423 | pfll_dev = (struct fll_device *)pargs; |
410 | board_obj_fll_ptr = (struct fll_device *)board_obj_ptr; | 424 | board_obj_fll_ptr = (struct fll_device *)board_obj_ptr; |
@@ -446,8 +460,9 @@ static u32 fll_device_init_pmudata_super(struct gk20a *g, | |||
446 | nvgpu_log_info(g, " "); | 460 | nvgpu_log_info(g, " "); |
447 | 461 | ||
448 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 462 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
449 | if (status != 0) | 463 | if (status != 0) { |
450 | return status; | 464 | return status; |
465 | } | ||
451 | 466 | ||
452 | pfll_dev = (struct fll_device *)board_obj_ptr; | 467 | pfll_dev = (struct fll_device *)board_obj_ptr; |
453 | perf_pmu_data = (struct nv_pmu_clk_clk_fll_device_boardobj_set *) | 468 | perf_pmu_data = (struct nv_pmu_clk_clk_fll_device_boardobj_set *) |