gpu: nvgpu: Add dGPU clocks support

JIRA DNVGPU-42

Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5
Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1205850
(cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114)
Reviewed-on: http://git-master/r/1227257
GVS: Gerrit_Virtual_Submit

1 files changed, 94 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_domain.h b/drivers/gpu/nvgpu/clk/clk_domain.h
new file mode 100644
index 00000000..94d612a7
--- /dev/null
+++ b/drivers/gpu/nvgpu/clk/clk_domain.h
@@ -0,0 +1,94 @@
+/*
+* Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms and conditions of the GNU General Public License,
+* version 2, as published by the Free Software Foundation.
+*
+* This program is distributed in the hope it will be useful, but WITHOUT
+* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+* FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+* more details.
+*/
+
+#ifndef _CLKDOMAIN_H_
+#define _CLKDOMAIN_H_
+
+#include "ctrl/ctrlclk.h"
+#include "ctrl/ctrlboardobj.h"
+#include "pmuif/gpmuifclk.h"
+#include "boardobj/boardobjgrp_e32.h"
+#include "boardobj/boardobjgrpmask.h"
+
+struct clk_domains;
+struct clk_domain;
+
+/*data and function definition to talk to driver*/
+u32 clk_domain_sw_setup(struct gk20a *g);
+u32 clk_domain_pmu_setup(struct gk20a *g);
+typedef u32 clkproglink(struct gk20a *g, struct clk_pmupstate *pclk,
+                        struct clk_domain *pdomain);
+struct clk_domains {
+        struct boardobjgrp_e32 super;
+        u8 n_num_entries;
+        u8 version;
+        bool b_enforce_vf_monotonicity;
+        u32 vbios_domains;
+        struct boardobjgrpmask_e32 prog_domains_mask;
+        struct boardobjgrpmask_e32 master_domains_mask;
+        u16 cntr_sampling_periodms;
+        struct ctrl_clk_clk_delta  deltas;
+
+        struct clk_domain *ordered_noise_aware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+
+        struct clk_domain *ordered_noise_unaware_list[CTRL_BOARDOBJ_MAX_BOARD_OBJECTS];
+};
+
+struct clk_domain {
+        struct boardobj super;
+        u32 api_domain;
+        u32 part_mask;
+        u8 domain;
+        u8 perf_domain_index;
+        u8 perf_domain_grp_idx;
+        u8 ratio_domain;
+        u8 usage;
+        clkproglink *clkdomainclkproglink;
+};
+
+struct clk_domain_3x {
+        struct clk_domain super;
+        bool b_noise_aware_capable;
+};
+
+struct clk_domain_3x_fixed {
+        struct clk_domain_3x super;
+        u16  freq_mhz;
+};
+
+struct clk_domain_3x_prog {
+        struct clk_domain_3x super;
+        u8  clk_prog_idx_first;
+        u8  clk_prog_idx_last;
+        u8 noise_unaware_ordering_index;
+        u8 noise_aware_ordering_index;
+        bool b_force_noise_unaware_ordering;
+        int factory_offset_khz;
+        short freq_delta_min_mhz;
+        short freq_delta_max_mhz;
+        struct ctrl_clk_clk_delta deltas;
+};
+
+struct clk_domain_3x_master {
+        struct clk_domain_3x_prog super;
+        u32 slave_idxs_mask;
+};
+
+struct clk_domain_3x_slave {
+        struct clk_domain_3x_prog super;
+        u8 master_idx;
+};
+
+u32 clk_domain_clk_prog_link(struct gk20a *g, struct clk_pmupstate *pclk);
+
+#endif