diff options
author | Srirangan <smadhavan@nvidia.com> | 2018-09-04 06:46:20 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-05 23:38:33 -0400 |
commit | ef851272e5201f343c9b287a9eacfc25d4912276 (patch) | |
tree | 2c7f85f168258e8b8779dd3ef32f1b18621fa6a7 /drivers/gpu/nvgpu/clk/clk_domain.c | |
parent | 78b4ab269f5d733c8b540a6a75db1f390172cc29 (diff) |
gpu: nvgpu: clk: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.
JIRA NVGPU-671
Change-Id: I228f04adea809e1dd4e6826bf1a04f051a533102
Signed-off-by: Srirangan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796831
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_domain.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_domain.c | 143 |
1 files changed, 95 insertions, 48 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c index 822bba2c..9f17d199 100644 --- a/drivers/gpu/nvgpu/clk/clk_domain.c +++ b/drivers/gpu/nvgpu/clk/clk_domain.c | |||
@@ -74,34 +74,48 @@ static u32 clktranslatehalmumsettoapinumset(u32 clkhaldomains) | |||
74 | { | 74 | { |
75 | u32 clkapidomains = 0; | 75 | u32 clkapidomains = 0; |
76 | 76 | ||
77 | if (clkhaldomains & BIT(clkwhich_gpcclk)) | 77 | if (clkhaldomains & BIT(clkwhich_gpcclk)) { |
78 | clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK; | 78 | clkapidomains |= CTRL_CLK_DOMAIN_GPCCLK; |
79 | if (clkhaldomains & BIT(clkwhich_xbarclk)) | 79 | } |
80 | if (clkhaldomains & BIT(clkwhich_xbarclk)) { | ||
80 | clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK; | 81 | clkapidomains |= CTRL_CLK_DOMAIN_XBARCLK; |
81 | if (clkhaldomains & BIT(clkwhich_sysclk)) | 82 | } |
83 | if (clkhaldomains & BIT(clkwhich_sysclk)) { | ||
82 | clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK; | 84 | clkapidomains |= CTRL_CLK_DOMAIN_SYSCLK; |
83 | if (clkhaldomains & BIT(clkwhich_hubclk)) | 85 | } |
86 | if (clkhaldomains & BIT(clkwhich_hubclk)) { | ||
84 | clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK; | 87 | clkapidomains |= CTRL_CLK_DOMAIN_HUBCLK; |
85 | if (clkhaldomains & BIT(clkwhich_hostclk)) | 88 | } |
89 | if (clkhaldomains & BIT(clkwhich_hostclk)) { | ||
86 | clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK; | 90 | clkapidomains |= CTRL_CLK_DOMAIN_HOSTCLK; |
87 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) | 91 | } |
92 | if (clkhaldomains & BIT(clkwhich_gpc2clk)) { | ||
88 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; | 93 | clkapidomains |= CTRL_CLK_DOMAIN_GPC2CLK; |
89 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) | 94 | } |
95 | if (clkhaldomains & BIT(clkwhich_xbar2clk)) { | ||
90 | clkapidomains |= CTRL_CLK_DOMAIN_XBAR2CLK; | 96 | clkapidomains |= CTRL_CLK_DOMAIN_XBAR2CLK; |
91 | if (clkhaldomains & BIT(clkwhich_sys2clk)) | 97 | } |
98 | if (clkhaldomains & BIT(clkwhich_sys2clk)) { | ||
92 | clkapidomains |= CTRL_CLK_DOMAIN_SYS2CLK; | 99 | clkapidomains |= CTRL_CLK_DOMAIN_SYS2CLK; |
93 | if (clkhaldomains & BIT(clkwhich_hub2clk)) | 100 | } |
101 | if (clkhaldomains & BIT(clkwhich_hub2clk)) { | ||
94 | clkapidomains |= CTRL_CLK_DOMAIN_HUB2CLK; | 102 | clkapidomains |= CTRL_CLK_DOMAIN_HUB2CLK; |
95 | if (clkhaldomains & BIT(clkwhich_pwrclk)) | 103 | } |
104 | if (clkhaldomains & BIT(clkwhich_pwrclk)) { | ||
96 | clkapidomains |= CTRL_CLK_DOMAIN_PWRCLK; | 105 | clkapidomains |= CTRL_CLK_DOMAIN_PWRCLK; |
97 | if (clkhaldomains & BIT(clkwhich_pciegenclk)) | 106 | } |
107 | if (clkhaldomains & BIT(clkwhich_pciegenclk)) { | ||
98 | clkapidomains |= CTRL_CLK_DOMAIN_PCIEGENCLK; | 108 | clkapidomains |= CTRL_CLK_DOMAIN_PCIEGENCLK; |
99 | if (clkhaldomains & BIT(clkwhich_mclk)) | 109 | } |
110 | if (clkhaldomains & BIT(clkwhich_mclk)) { | ||
100 | clkapidomains |= CTRL_CLK_DOMAIN_MCLK; | 111 | clkapidomains |= CTRL_CLK_DOMAIN_MCLK; |
101 | if (clkhaldomains & BIT(clkwhich_nvdclk)) | 112 | } |
113 | if (clkhaldomains & BIT(clkwhich_nvdclk)) { | ||
102 | clkapidomains |= CTRL_CLK_DOMAIN_NVDCLK; | 114 | clkapidomains |= CTRL_CLK_DOMAIN_NVDCLK; |
103 | if (clkhaldomains & BIT(clkwhich_dispclk)) | 115 | } |
116 | if (clkhaldomains & BIT(clkwhich_dispclk)) { | ||
104 | clkapidomains |= CTRL_CLK_DOMAIN_DISPCLK; | 117 | clkapidomains |= CTRL_CLK_DOMAIN_DISPCLK; |
118 | } | ||
105 | 119 | ||
106 | return clkapidomains; | 120 | return clkapidomains; |
107 | } | 121 | } |
@@ -131,10 +145,11 @@ static u32 _clk_domains_pmudatainit_3x(struct gk20a *g, | |||
131 | pset->b_debug_mode = false; | 145 | pset->b_debug_mode = false; |
132 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; | 146 | pset->b_enforce_vf_monotonicity = pdomains->b_enforce_vf_monotonicity; |
133 | pset->b_enforce_vf_smoothening = pdomains->b_enforce_vf_smoothening; | 147 | pset->b_enforce_vf_smoothening = pdomains->b_enforce_vf_smoothening; |
134 | if (g->ops.clk.split_rail_support) | 148 | if (g->ops.clk.split_rail_support) { |
135 | pset->volt_rails_max = 2; | 149 | pset->volt_rails_max = 2; |
136 | else | 150 | } else { |
137 | pset->volt_rails_max = 1; | 151 | pset->volt_rails_max = 1; |
152 | } | ||
138 | status = boardobjgrpmask_export( | 153 | status = boardobjgrpmask_export( |
139 | &pdomains->master_domains_mask.super, | 154 | &pdomains->master_domains_mask.super, |
140 | pdomains->master_domains_mask.super.bitcount, | 155 | pdomains->master_domains_mask.super.bitcount, |
@@ -160,8 +175,9 @@ static u32 _clk_domains_pmudata_instget(struct gk20a *g, | |||
160 | 175 | ||
161 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 176 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
162 | if (((u32)BIT(idx) & | 177 | if (((u32)BIT(idx) & |
163 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) | 178 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { |
164 | return -EINVAL; | 179 | return -EINVAL; |
180 | } | ||
165 | 181 | ||
166 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) | 182 | *ppboardobjpmudata = (struct nv_pmu_boardobj *) |
167 | &pgrp_set->objects[idx].data.board_obj; | 183 | &pgrp_set->objects[idx].data.board_obj; |
@@ -222,8 +238,9 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
222 | sizeof(struct ctrl_clk_clk_delta)); | 238 | sizeof(struct ctrl_clk_clk_delta)); |
223 | 239 | ||
224 | status = devinit_get_clocks_table(g, pclkdomainobjs); | 240 | status = devinit_get_clocks_table(g, pclkdomainobjs); |
225 | if (status) | 241 | if (status) { |
226 | goto done; | 242 | goto done; |
243 | } | ||
227 | 244 | ||
228 | BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super), | 245 | BOARDOBJGRP_FOR_EACH(&(pclkdomainobjs->super.super), |
229 | struct clk_domain *, pdomain, i) { | 246 | struct clk_domain *, pdomain, i) { |
@@ -232,16 +249,18 @@ u32 clk_domain_sw_setup(struct gk20a *g) | |||
232 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) { | 249 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG)) { |
233 | status = boardobjgrpmask_bitset( | 250 | status = boardobjgrpmask_bitset( |
234 | &pclkdomainobjs->prog_domains_mask.super, i); | 251 | &pclkdomainobjs->prog_domains_mask.super, i); |
235 | if (status) | 252 | if (status) { |
236 | goto done; | 253 | goto done; |
254 | } | ||
237 | } | 255 | } |
238 | 256 | ||
239 | if (pdomain->super.implements(g, &pdomain->super, | 257 | if (pdomain->super.implements(g, &pdomain->super, |
240 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) { | 258 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER)) { |
241 | status = boardobjgrpmask_bitset( | 259 | status = boardobjgrpmask_bitset( |
242 | &pclkdomainobjs->master_domains_mask.super, i); | 260 | &pclkdomainobjs->master_domains_mask.super, i); |
243 | if (status) | 261 | if (status) { |
244 | goto done; | 262 | goto done; |
263 | } | ||
245 | } | 264 | } |
246 | 265 | ||
247 | if (pdomain->super.implements(g, &pdomain->super, | 266 | if (pdomain->super.implements(g, &pdomain->super, |
@@ -271,8 +290,9 @@ u32 clk_domain_pmu_setup(struct gk20a *g) | |||
271 | 290 | ||
272 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; | 291 | pboardobjgrp = &g->clk_pmu.clk_domainobjs.super.super; |
273 | 292 | ||
274 | if (!pboardobjgrp->bconstructed) | 293 | if (!pboardobjgrp->bconstructed) { |
275 | return -EINVAL; | 294 | return -EINVAL; |
295 | } | ||
276 | 296 | ||
277 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); | 297 | status = pboardobjgrp->pmuinithandle(g, pboardobjgrp); |
278 | 298 | ||
@@ -511,8 +531,9 @@ static u32 clk_domain_construct_super(struct gk20a *g, | |||
511 | status = boardobj_construct_super(g, ppboardobj, | 531 | status = boardobj_construct_super(g, ppboardobj, |
512 | size, pargs); | 532 | size, pargs); |
513 | 533 | ||
514 | if (status) | 534 | if (status) { |
515 | return -EINVAL; | 535 | return -EINVAL; |
536 | } | ||
516 | 537 | ||
517 | pdomain = (struct clk_domain *)*ppboardobj; | 538 | pdomain = (struct clk_domain *)*ppboardobj; |
518 | 539 | ||
@@ -547,8 +568,9 @@ static u32 _clk_domain_pmudatainit_3x(struct gk20a *g, | |||
547 | nvgpu_log_info(g, " "); | 568 | nvgpu_log_info(g, " "); |
548 | 569 | ||
549 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); | 570 | status = clk_domain_pmudatainit_super(g, board_obj_ptr, ppmudata); |
550 | if (status != 0) | 571 | if (status != 0) { |
551 | return status; | 572 | return status; |
573 | } | ||
552 | 574 | ||
553 | pclk_domain_3x = (struct clk_domain_3x *)board_obj_ptr; | 575 | pclk_domain_3x = (struct clk_domain_3x *)board_obj_ptr; |
554 | 576 | ||
@@ -572,8 +594,9 @@ static u32 clk_domain_construct_3x(struct gk20a *g, | |||
572 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X); | 594 | ptmpobj->type_mask = BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X); |
573 | status = clk_domain_construct_super(g, ppboardobj, | 595 | status = clk_domain_construct_super(g, ppboardobj, |
574 | size, pargs); | 596 | size, pargs); |
575 | if (status) | 597 | if (status) { |
576 | return -EINVAL; | 598 | return -EINVAL; |
599 | } | ||
577 | 600 | ||
578 | pdomain = (struct clk_domain_3x *)*ppboardobj; | 601 | pdomain = (struct clk_domain_3x *)*ppboardobj; |
579 | 602 | ||
@@ -601,8 +624,9 @@ static u32 clkdomainclkproglink_3x_prog(struct gk20a *g, | |||
601 | i <= p3xprog->clk_prog_idx_last; | 624 | i <= p3xprog->clk_prog_idx_last; |
602 | i++) { | 625 | i++) { |
603 | pprog = CLK_CLK_PROG_GET(pclk, i); | 626 | pprog = CLK_CLK_PROG_GET(pclk, i); |
604 | if (pprog == NULL) | 627 | if (pprog == NULL) { |
605 | status = -EINVAL; | 628 | status = -EINVAL; |
629 | } | ||
606 | } | 630 | } |
607 | return status; | 631 | return status; |
608 | } | 632 | } |
@@ -621,11 +645,13 @@ static int clkdomaingetslaveclk(struct gk20a *g, | |||
621 | 645 | ||
622 | nvgpu_log_info(g, " "); | 646 | nvgpu_log_info(g, " "); |
623 | 647 | ||
624 | if (pclkmhz == NULL) | 648 | if (pclkmhz == NULL) { |
625 | return -EINVAL; | 649 | return -EINVAL; |
650 | } | ||
626 | 651 | ||
627 | if (masterclkmhz == 0) | 652 | if (masterclkmhz == 0) { |
628 | return -EINVAL; | 653 | return -EINVAL; |
654 | } | ||
629 | 655 | ||
630 | slaveidx = BOARDOBJ_GET_IDX(pdomain); | 656 | slaveidx = BOARDOBJ_GET_IDX(pdomain); |
631 | p3xmaster = (struct clk_domain_3x_master *) | 657 | p3xmaster = (struct clk_domain_3x_master *) |
@@ -662,11 +688,13 @@ static int clkdomainvfsearch(struct gk20a *g, | |||
662 | 688 | ||
663 | nvgpu_log_info(g, " "); | 689 | nvgpu_log_info(g, " "); |
664 | 690 | ||
665 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) | 691 | if ((pclkmhz == NULL) || (pvoltuv == NULL)) { |
666 | return -EINVAL; | 692 | return -EINVAL; |
693 | } | ||
667 | 694 | ||
668 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) | 695 | if ((*pclkmhz != 0) && (*pvoltuv != 0)) { |
669 | return -EINVAL; | 696 | return -EINVAL; |
697 | } | ||
670 | 698 | ||
671 | bestclkmhz = *pclkmhz; | 699 | bestclkmhz = *pclkmhz; |
672 | bestvoltuv = *pvoltuv; | 700 | bestvoltuv = *pvoltuv; |
@@ -749,15 +777,18 @@ static u32 clkdomaingetfpoints | |||
749 | 777 | ||
750 | nvgpu_log_info(g, " "); | 778 | nvgpu_log_info(g, " "); |
751 | 779 | ||
752 | if (pfpointscount == NULL) | 780 | if (pfpointscount == NULL) { |
753 | return -EINVAL; | 781 | return -EINVAL; |
782 | } | ||
754 | 783 | ||
755 | if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0)) | 784 | if ((pfreqpointsinmhz == NULL) && (*pfpointscount != 0)) { |
756 | return -EINVAL; | 785 | return -EINVAL; |
786 | } | ||
757 | 787 | ||
758 | if (pdomain->super.implements(g, &pdomain->super, | 788 | if (pdomain->super.implements(g, &pdomain->super, |
759 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE)) | 789 | CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE)) { |
760 | return -EINVAL; | 790 | return -EINVAL; |
791 | } | ||
761 | 792 | ||
762 | freqpointsdata = pfreqpointsinmhz; | 793 | freqpointsdata = pfreqpointsinmhz; |
763 | totalcount = 0; | 794 | totalcount = 0; |
@@ -779,8 +810,9 @@ static u32 clkdomaingetfpoints | |||
779 | if (*pfpointscount) { | 810 | if (*pfpointscount) { |
780 | remainingcount -= fpointscount; | 811 | remainingcount -= fpointscount; |
781 | fpointscount = remainingcount; | 812 | fpointscount = remainingcount; |
782 | } else | 813 | } else { |
783 | fpointscount = 0; | 814 | fpointscount = 0; |
815 | } | ||
784 | 816 | ||
785 | } | 817 | } |
786 | 818 | ||
@@ -802,8 +834,9 @@ static u32 _clk_domain_pmudatainit_3x_prog(struct gk20a *g, | |||
802 | nvgpu_log_info(g, " "); | 834 | nvgpu_log_info(g, " "); |
803 | 835 | ||
804 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 836 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
805 | if (status != 0) | 837 | if (status != 0) { |
806 | return status; | 838 | return status; |
839 | } | ||
807 | 840 | ||
808 | pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr; | 841 | pclk_domain_3x_prog = (struct clk_domain_3x_prog *)board_obj_ptr; |
809 | 842 | ||
@@ -839,8 +872,9 @@ static u32 clk_domain_construct_3x_prog(struct gk20a *g, | |||
839 | 872 | ||
840 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG); | 873 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_PROG); |
841 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); | 874 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); |
842 | if (status) | 875 | if (status) { |
843 | return -EINVAL; | 876 | return -EINVAL; |
877 | } | ||
844 | 878 | ||
845 | pdomain = (struct clk_domain_3x_prog *)*ppboardobj; | 879 | pdomain = (struct clk_domain_3x_prog *)*ppboardobj; |
846 | 880 | ||
@@ -882,8 +916,9 @@ static u32 _clk_domain_pmudatainit_3x_slave(struct gk20a *g, | |||
882 | nvgpu_log_info(g, " "); | 916 | nvgpu_log_info(g, " "); |
883 | 917 | ||
884 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 918 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
885 | if (status != 0) | 919 | if (status != 0) { |
886 | return status; | 920 | return status; |
921 | } | ||
887 | 922 | ||
888 | pclk_domain_3x_slave = (struct clk_domain_3x_slave *)board_obj_ptr; | 923 | pclk_domain_3x_slave = (struct clk_domain_3x_slave *)board_obj_ptr; |
889 | 924 | ||
@@ -905,13 +940,15 @@ static u32 clk_domain_construct_3x_slave(struct gk20a *g, | |||
905 | (struct clk_domain_3x_slave *)pargs; | 940 | (struct clk_domain_3x_slave *)pargs; |
906 | u32 status = 0; | 941 | u32 status = 0; |
907 | 942 | ||
908 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) | 943 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE) { |
909 | return -EINVAL; | 944 | return -EINVAL; |
945 | } | ||
910 | 946 | ||
911 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE); | 947 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_SLAVE); |
912 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); | 948 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); |
913 | if (status) | 949 | if (status) { |
914 | return -EINVAL; | 950 | return -EINVAL; |
951 | } | ||
915 | 952 | ||
916 | pdomain = (struct clk_domain_3x_slave *)*ppboardobj; | 953 | pdomain = (struct clk_domain_3x_slave *)*ppboardobj; |
917 | 954 | ||
@@ -941,8 +978,9 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
941 | nvgpu_log_info(g, " "); | 978 | nvgpu_log_info(g, " "); |
942 | 979 | ||
943 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); | 980 | status = clkdomainclkproglink_3x_prog(g, pclk, pdomain); |
944 | if (status) | 981 | if (status) { |
945 | goto done; | 982 | goto done; |
983 | } | ||
946 | 984 | ||
947 | /* Iterate over the set of CLK_PROGs pointed at by this domain.*/ | 985 | /* Iterate over the set of CLK_PROGs pointed at by this domain.*/ |
948 | for (i = p3xmaster->super.clk_prog_idx_first; | 986 | for (i = p3xmaster->super.clk_prog_idx_first; |
@@ -960,8 +998,9 @@ static u32 clkdomainclkproglink_3x_master(struct gk20a *g, | |||
960 | pprog1xmaster = (struct clk_prog_1x_master *)pprog; | 998 | pprog1xmaster = (struct clk_prog_1x_master *)pprog; |
961 | status = pprog1xmaster->vfflatten(g, pclk, pprog1xmaster, | 999 | status = pprog1xmaster->vfflatten(g, pclk, pprog1xmaster, |
962 | BOARDOBJ_GET_IDX(p3xmaster), &freq_max_last_mhz); | 1000 | BOARDOBJ_GET_IDX(p3xmaster), &freq_max_last_mhz); |
963 | if (status) | 1001 | if (status) { |
964 | goto done; | 1002 | goto done; |
1003 | } | ||
965 | } | 1004 | } |
966 | done: | 1005 | done: |
967 | nvgpu_log_info(g, "done status %x", status); | 1006 | nvgpu_log_info(g, "done status %x", status); |
@@ -979,8 +1018,9 @@ static u32 _clk_domain_pmudatainit_3x_master(struct gk20a *g, | |||
979 | nvgpu_log_info(g, " "); | 1018 | nvgpu_log_info(g, " "); |
980 | 1019 | ||
981 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); | 1020 | status = _clk_domain_pmudatainit_3x_prog(g, board_obj_ptr, ppmudata); |
982 | if (status != 0) | 1021 | if (status != 0) { |
983 | return status; | 1022 | return status; |
1023 | } | ||
984 | 1024 | ||
985 | pclk_domain_3x_master = (struct clk_domain_3x_master *)board_obj_ptr; | 1025 | pclk_domain_3x_master = (struct clk_domain_3x_master *)board_obj_ptr; |
986 | 1026 | ||
@@ -1000,13 +1040,15 @@ static u32 clk_domain_construct_3x_master(struct gk20a *g, | |||
1000 | struct clk_domain_3x_master *pdomain; | 1040 | struct clk_domain_3x_master *pdomain; |
1001 | u32 status = 0; | 1041 | u32 status = 0; |
1002 | 1042 | ||
1003 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER) | 1043 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER) { |
1004 | return -EINVAL; | 1044 | return -EINVAL; |
1045 | } | ||
1005 | 1046 | ||
1006 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER); | 1047 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_MASTER); |
1007 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); | 1048 | status = clk_domain_construct_3x_prog(g, ppboardobj, size, pargs); |
1008 | if (status) | 1049 | if (status) { |
1009 | return -EINVAL; | 1050 | return -EINVAL; |
1051 | } | ||
1010 | 1052 | ||
1011 | pdomain = (struct clk_domain_3x_master *)*ppboardobj; | 1053 | pdomain = (struct clk_domain_3x_master *)*ppboardobj; |
1012 | 1054 | ||
@@ -1039,8 +1081,9 @@ static u32 _clk_domain_pmudatainit_3x_fixed(struct gk20a *g, | |||
1039 | nvgpu_log_info(g, " "); | 1081 | nvgpu_log_info(g, " "); |
1040 | 1082 | ||
1041 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); | 1083 | status = _clk_domain_pmudatainit_3x(g, board_obj_ptr, ppmudata); |
1042 | if (status != 0) | 1084 | if (status != 0) { |
1043 | return status; | 1085 | return status; |
1086 | } | ||
1044 | 1087 | ||
1045 | pclk_domain_3x_fixed = (struct clk_domain_3x_fixed *)board_obj_ptr; | 1088 | pclk_domain_3x_fixed = (struct clk_domain_3x_fixed *)board_obj_ptr; |
1046 | 1089 | ||
@@ -1062,13 +1105,15 @@ static u32 clk_domain_construct_3x_fixed(struct gk20a *g, | |||
1062 | (struct clk_domain_3x_fixed *)pargs; | 1105 | (struct clk_domain_3x_fixed *)pargs; |
1063 | u32 status = 0; | 1106 | u32 status = 0; |
1064 | 1107 | ||
1065 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED) | 1108 | if (BOARDOBJ_GET_TYPE(pargs) != CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED) { |
1066 | return -EINVAL; | 1109 | return -EINVAL; |
1110 | } | ||
1067 | 1111 | ||
1068 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED); | 1112 | ptmpobj->type_mask |= BIT(CTRL_CLK_CLK_DOMAIN_TYPE_3X_FIXED); |
1069 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); | 1113 | status = clk_domain_construct_3x(g, ppboardobj, size, pargs); |
1070 | if (status) | 1114 | if (status) { |
1071 | return -EINVAL; | 1115 | return -EINVAL; |
1116 | } | ||
1072 | 1117 | ||
1073 | pdomain = (struct clk_domain_3x_fixed *)*ppboardobj; | 1118 | pdomain = (struct clk_domain_3x_fixed *)*ppboardobj; |
1074 | 1119 | ||
@@ -1109,8 +1154,9 @@ static struct clk_domain *construct_clk_domain(struct gk20a *g, void *pargs) | |||
1109 | return NULL; | 1154 | return NULL; |
1110 | } | 1155 | } |
1111 | 1156 | ||
1112 | if (status) | 1157 | if (status) { |
1113 | return NULL; | 1158 | return NULL; |
1159 | } | ||
1114 | 1160 | ||
1115 | nvgpu_log_info(g, " Done"); | 1161 | nvgpu_log_info(g, " Done"); |
1116 | 1162 | ||
@@ -1128,8 +1174,9 @@ static u32 clk_domain_pmudatainit_super(struct gk20a *g, | |||
1128 | nvgpu_log_info(g, " "); | 1174 | nvgpu_log_info(g, " "); |
1129 | 1175 | ||
1130 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); | 1176 | status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata); |
1131 | if (status != 0) | 1177 | if (status != 0) { |
1132 | return status; | 1178 | return status; |
1179 | } | ||
1133 | 1180 | ||
1134 | pclk_domain = (struct clk_domain *)board_obj_ptr; | 1181 | pclk_domain = (struct clk_domain *)board_obj_ptr; |
1135 | 1182 | ||