nvgpu: gpu: arbiter for vf switch management

JIRA DNVGPU-143

The arbiter is charged with selecting the proper
frequencies when multiple applications submit
simultaneously clock change requests

On the current implementation, the arbiter guarantees
that the selected frequency will be always higher
or equal to the request, as long as the request is
in range.

The current code is not yet realtime friendly, as
requests are not pre-allocated.

Summary of changes:
(1) pstate/vf switch no longer selects boot frequency
(2) changed mclk code change to accept input freq
(3) added arbiter
(4) now a single session can submit concurrent requests
the last request is the one that applies for that
session
(5) modified locking mechanism to reduce lock contention
(6) Added callback to notify the arbiter that the VF
table has changed and is no longer valid (PMU/Thermals
must call this when VF table is invalid)
(7) changed internal API to work with MHz
(8) added debugfs for stats

Change-Id: I6a7b05c9447761e8536f84ef86b5ab0793164d63
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: http://git-master/r/1239461
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1267120
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 14 insertions, 12 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_arb.h b/drivers/gpu/nvgpu/clk/clk_arb.h
index 95749369..717cca9b 100644
--- a/drivers/gpu/nvgpu/clk/clk_arb.h
+++ b/drivers/gpu/nvgpu/clk/clk_arb.h
@@ -22,13 +22,13 @@ struct nvgpu_clk_session;
 int nvgpu_clk_arb_init_arbiter(struct gk20a *g);
 
 int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
-                u64 *min_hz, u64 *max_hz);
+                u16 *min_mhz, u16 *max_mhz);
 
-int nvgpu_clk_arb_get_arbiter_actual_hz(struct gk20a *g,
-                u32 api_domain, u64 *actual_hz);
+int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
+                u32 api_domain, u16 *actual_mhz);
 
-int nvgpu_clk_arb_get_arbiter_effective_hz(struct gk20a *g,
-                u32 api_domain, u64 *actual_hz);
+int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
+                u32 api_domain, u16 *effective_mhz);
 
 int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
         u32 api_domain, u32 *max_points, u16 *fpoints);
@@ -46,19 +46,21 @@ int nvgpu_clk_arb_init_session(struct gk20a *g,
 void nvgpu_clk_arb_release_session(struct gk20a *g,
                 struct nvgpu_clk_session *session);
 
-int nvgpu_clk_arb_apply_session_constraints(struct gk20a *g,
-        struct nvgpu_clk_session *session, int *completion_fd);
+int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
+        struct nvgpu_clk_session *session, int request_fd);
 
-int nvgpu_clk_arb_set_session_target_hz(struct nvgpu_clk_session *session,
-                u32 api_domain, u64 target_hz);
+int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
+                int fd, u32 api_domain, u16 target_mhz);
 
-int nvgpu_clk_arb_get_session_target_hz(struct nvgpu_clk_session *session,
-                u32 api_domain, u64 *target_hz);
+int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
+                u32 api_domain, u16 *target_mhz);
 
 int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
         struct nvgpu_clk_session *session, int *event_fd);
 
+int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
+        struct nvgpu_clk_session *session, int *event_fd);
 
-
+void nvgpu_clk_arb_schedule_vftable_update(struct gk20a *g);
 #endif /* _CLK_ARB_H_ */