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authorVijayakumar <vsubbu@nvidia.com>2016-11-21 07:19:13 -0500
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:52 -0500
commit8edfc9ee67d8c346310b2ad653754440719a29d7 (patch)
tree01d2c4f2835034980a665373283c89131773a208 /drivers/gpu/nvgpu/clk/clk_arb.c
parent8cc67f60644a117eec868fc1b11da9a60d2915d7 (diff)
gpu: nvgpu: set p state floor for sys and xbar clk
bug 200254784 If XBAR and SYS clocks for a given GPC clock point is lower than minimum value mentioned in P state set the floor to minimum value mentioned in p state. it was set to value based ratio of a GPC clk value in VF table which can give value higher than one mentioned in p state. Ignore ratio and just set to p state value Change-Id: I9f7cd1d5842d057aff6d8243a31ab503ce35a8ca Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1257251 Reviewed-by: Automatic_Commit_Validation_User (cherry picked from commit 5798680286967ff999f674bedd4fc0411615f914) Reviewed-on: http://git-master/r/1270949 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_arb.c')
-rw-r--r--drivers/gpu/nvgpu/clk/clk_arb.c29
1 files changed, 4 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
index b816a570..ee75ce64 100644
--- a/drivers/gpu/nvgpu/clk/clk_arb.c
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -617,7 +617,6 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
617 617
618 table->gpc2clk_points[j].gpc_mhz = 618 table->gpc2clk_points[j].gpc_mhz =
619 arb->gpc2clk_f_points[i]; 619 arb->gpc2clk_f_points[i];
620
621 setfllclk.gpc2clkmhz = arb->gpc2clk_f_points[i]; 620 setfllclk.gpc2clkmhz = arb->gpc2clk_f_points[i];
622 status = clk_get_fll_clks(g, &setfllclk); 621 status = clk_get_fll_clks(g, &setfllclk);
623 if (status < 0) { 622 if (status < 0) {
@@ -626,7 +625,6 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
626 goto exit_vf_table; 625 goto exit_vf_table;
627 } 626 }
628 627
629
630 table->gpc2clk_points[j].sys_mhz = 628 table->gpc2clk_points[j].sys_mhz =
631 setfllclk.sys2clkmhz; 629 setfllclk.sys2clkmhz;
632 table->gpc2clk_points[j].xbar_mhz = 630 table->gpc2clk_points[j].xbar_mhz =
@@ -653,7 +651,6 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
653 651
654 /* Second pass */ 652 /* Second pass */
655 for (i = 0, j = 0; i < table->gpc2clk_num_points; i++) { 653 for (i = 0, j = 0; i < table->gpc2clk_num_points; i++) {
656 struct set_fll_clk setfllclk;
657 654
658 u16 alt_gpc2clk = table->gpc2clk_points[i].gpc_mhz; 655 u16 alt_gpc2clk = table->gpc2clk_points[i].gpc_mhz;
659 gpc2clk_voltuv = gpc2clk_voltuv_sram = 0; 656 gpc2clk_voltuv = gpc2clk_voltuv_sram = 0;
@@ -673,9 +670,9 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
673 if (table->gpc2clk_points[j].sys_mhz >= 670 if (table->gpc2clk_points[j].sys_mhz >=
674 p5_info->min_mhz) { 671 p5_info->min_mhz) {
675 672
673
676 table->gpc2clk_points[i].sys_mhz = 674 table->gpc2clk_points[i].sys_mhz =
677 table->gpc2clk_points[j]. 675 p5_info->min_mhz;
678 sys_mhz;
679 676
680 alt_gpc2clk = alt_gpc2clk < 677 alt_gpc2clk = alt_gpc2clk <
681 table->gpc2clk_points[j]. 678 table->gpc2clk_points[j].
@@ -709,8 +706,8 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
709 p5_info->min_mhz) { 706 p5_info->min_mhz) {
710 707
711 table->gpc2clk_points[i].xbar_mhz = 708 table->gpc2clk_points[i].xbar_mhz =
712 table->gpc2clk_points[j]. 709 p5_info->min_mhz;
713 xbar_mhz; 710
714 alt_gpc2clk = alt_gpc2clk < 711 alt_gpc2clk = alt_gpc2clk <
715 table->gpc2clk_points[j]. 712 table->gpc2clk_points[j].
716 gpc_mhz ? 713 gpc_mhz ?
@@ -728,24 +725,6 @@ static int nvgpu_clk_arb_update_vf_table(struct nvgpu_clk_arb *arb)
728 } 725 }
729 } 726 }
730 727
731 /* alternate gpc2clk clock has been requested, we need to
732 * calculate new ratios */
733 if (alt_gpc2clk != table->gpc2clk_points[i].gpc_mhz) {
734 setfllclk.gpc2clkmhz = alt_gpc2clk;
735
736 status = clk_get_fll_clks(g, &setfllclk);
737 if (status < 0) {
738 gk20a_err(dev_from_gk20a(g),
739 "failed to get GPC2CLK slave clocks");
740 goto exit_vf_table;
741 }
742
743 table->gpc2clk_points[i].sys_mhz =
744 setfllclk.sys2clkmhz;
745 table->gpc2clk_points[i].xbar_mhz =
746 setfllclk.xbar2clkmhz;
747 }
748
749 /* Calculate voltages */ 728 /* Calculate voltages */
750 status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPC2CLK, 729 status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPC2CLK,
751 &alt_gpc2clk, &gpc2clk_voltuv, 730 &alt_gpc2clk, &gpc2clk_voltuv,