diff options
author | Sourab Gupta <sourabg@nvidia.com> | 2018-05-04 05:44:33 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-18 02:34:45 -0400 |
commit | 5903094ffeaca10fd0f49c5eae41e2d511f940f6 (patch) | |
tree | 50d55a9bdcc2237236ed825cbcef61a848dab257 /drivers/gpu/nvgpu/clk/clk_arb.c | |
parent | c06c2c52ce4991f885fd30f76236038ed4933a3a (diff) |
gpu: nvgpu: add conversion function for clk domain
Add a conversion function for NVGPU_GPU_CLK_DOMAIN_*
defines present in uapi header.
This enables movement of related code to the OS agnostic
clk_arb.c
Jira VQRM-3741
Change-Id: I922d1cfb91d6a5dda644cf418f2f3815d975fcfd
Signed-off-by: Sourab Gupta <sourabg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1709653
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk_arb.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 128 |
1 files changed, 128 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index eaf9d8a5..8b499b16 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -1525,3 +1525,131 @@ void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock) | |||
1525 | else | 1525 | else |
1526 | nvgpu_mutex_release(&arb->pstate_lock); | 1526 | nvgpu_mutex_release(&arb->pstate_lock); |
1527 | } | 1527 | } |
1528 | |||
1529 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | ||
1530 | { | ||
1531 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
1532 | |||
1533 | switch (api_domain) { | ||
1534 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1535 | return (clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0; | ||
1536 | |||
1537 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1538 | return (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0; | ||
1539 | |||
1540 | default: | ||
1541 | return false; | ||
1542 | } | ||
1543 | } | ||
1544 | |||
1545 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
1546 | u16 *min_mhz, u16 *max_mhz) | ||
1547 | { | ||
1548 | int ret; | ||
1549 | |||
1550 | switch (api_domain) { | ||
1551 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1552 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1553 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | ||
1554 | return ret; | ||
1555 | |||
1556 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1557 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1558 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); | ||
1559 | if (!ret) { | ||
1560 | *min_mhz /= 2; | ||
1561 | *max_mhz /= 2; | ||
1562 | } | ||
1563 | return ret; | ||
1564 | |||
1565 | default: | ||
1566 | return -EINVAL; | ||
1567 | } | ||
1568 | } | ||
1569 | |||
1570 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | ||
1571 | u32 api_domain, u32 *max_points, u16 *fpoints) | ||
1572 | { | ||
1573 | int err; | ||
1574 | u32 i; | ||
1575 | |||
1576 | switch (api_domain) { | ||
1577 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1578 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | ||
1579 | max_points, fpoints); | ||
1580 | if (err || !fpoints) | ||
1581 | return err; | ||
1582 | for (i = 0; i < *max_points; i++) | ||
1583 | fpoints[i] /= 2; | ||
1584 | return 0; | ||
1585 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1586 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | ||
1587 | max_points, fpoints); | ||
1588 | default: | ||
1589 | return -EINVAL; | ||
1590 | } | ||
1591 | } | ||
1592 | |||
1593 | int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | ||
1594 | u32 api_domain, u16 *freq_mhz) | ||
1595 | { | ||
1596 | int err = 0; | ||
1597 | struct nvgpu_clk_arb_target *target = session->target; | ||
1598 | |||
1599 | switch (api_domain) { | ||
1600 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1601 | *freq_mhz = target->mclk; | ||
1602 | break; | ||
1603 | |||
1604 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1605 | *freq_mhz = target->gpc2clk / 2ULL; | ||
1606 | break; | ||
1607 | |||
1608 | default: | ||
1609 | *freq_mhz = 0; | ||
1610 | err = -EINVAL; | ||
1611 | } | ||
1612 | return err; | ||
1613 | } | ||
1614 | |||
1615 | int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | ||
1616 | u32 api_domain, u16 *freq_mhz) | ||
1617 | { | ||
1618 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
1619 | int err = 0; | ||
1620 | struct nvgpu_clk_arb_target *actual = arb->actual; | ||
1621 | |||
1622 | switch (api_domain) { | ||
1623 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1624 | *freq_mhz = actual->mclk; | ||
1625 | break; | ||
1626 | |||
1627 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1628 | *freq_mhz = actual->gpc2clk / 2ULL; | ||
1629 | break; | ||
1630 | |||
1631 | default: | ||
1632 | *freq_mhz = 0; | ||
1633 | err = -EINVAL; | ||
1634 | } | ||
1635 | return err; | ||
1636 | } | ||
1637 | |||
1638 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | ||
1639 | u32 api_domain, u16 *freq_mhz) | ||
1640 | { | ||
1641 | switch (api_domain) { | ||
1642 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1643 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / | ||
1644 | 1000000ULL; | ||
1645 | return 0; | ||
1646 | |||
1647 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1648 | *freq_mhz = g->ops.clk.measure_freq(g, | ||
1649 | CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL; | ||
1650 | return 0; | ||
1651 | |||
1652 | default: | ||
1653 | return -EINVAL; | ||
1654 | } | ||
1655 | } | ||