gpu: nvgpu: Selectively disable/enable CFC

clk_pmu_freq_controller_load used the default mask and affected
all the clock frequency controllers (CFC) which had their bits
set in the mask. We wish to enable/disable the CFCs in isolation
through debugfs. So we add a parameter(bit_idx) to the function
which will help affect only one CFC at a time

JIRA DNVGPU-207

DEPENDS ON: <http://git-master/r/1563302>

Change-Id: I233f52158b4a987bcc058a425380983dbe53fac8
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1563303
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c
index ac37d03f..8c27b613 100644
--- a/drivers/gpu/nvgpu/clk/clk_arb.c
+++ b/drivers/gpu/nvgpu/clk/clk_arb.c
@@ -1178,7 +1178,8 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work)
         nvgpu_mutex_acquire(&arb->pstate_lock);
         status = nvgpu_lpwr_disable_pg(g, false);
 
-        status = clk_pmu_freq_controller_load(g, false);
+        status = clk_pmu_freq_controller_load(g, false,
+                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL);
         if (status < 0) {
                 arb->status = status;
                 nvgpu_mutex_release(&arb->pstate_lock);
@@ -1209,7 +1210,8 @@ static void nvgpu_clk_arb_run_arbiter_cb(struct work_struct *work)
                 goto exit_arb;
         }
 
-        status = clk_pmu_freq_controller_load(g, true);
+        status = clk_pmu_freq_controller_load(g, true,
+                                         CTRL_CLK_CLK_FREQ_CONTROLLER_ID_ALL);
         if (status < 0) {
                 arb->status = status;
                 nvgpu_mutex_release(&arb->pstate_lock);