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authorVijayakumar <vsubbu@nvidia.com>2016-11-04 07:17:51 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:52 -0500
commit8cc67f60644a117eec868fc1b11da9a60d2915d7 (patch)
tree5b32619b84feed4d9925c519ffe1dac5fd7b3775 /drivers/gpu/nvgpu/clk/clk.h
parent30bf630bded30376a929345247b134b60db1c9f5 (diff)
gpu: nvgpu: add clock freq controller support
JIRA DNVGPU-170 1) Add clock frequency controller VBIOS structure definitions 2) Parse VBIOS tables and build boardobj structures for clock frequency controller. 3) send clock frequency controller data structures to PMU 4) implement public function to send load/unload command to pmu to enable/disable clock frequency controller support Change-Id: I2f37f6a94f342b6fcc71bb802e6e440a0a454486 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1248209 Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com> (cherry picked from commit ed3e27933f21e10b3d7a5257f1b751526945bd07) Reviewed-on: http://git-master/r/1270897 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk.h')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index 42cb9f7d..b173a09e 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -21,6 +21,7 @@
21#include "clk_prog.h" 21#include "clk_prog.h"
22#include "clk_vf_point.h" 22#include "clk_vf_point.h"
23#include "clk_mclk.h" 23#include "clk_mclk.h"
24#include "clk_freq_controller.h"
24#include "gk20a/gk20a.h" 25#include "gk20a/gk20a.h"
25 26
26#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10 27#define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
@@ -35,6 +36,7 @@ struct clk_pmupstate {
35 struct clk_progs clk_progobjs; 36 struct clk_progs clk_progobjs;
36 struct clk_vf_points clk_vf_pointobjs; 37 struct clk_vf_points clk_vf_pointobjs;
37 struct clk_mclk_state clk_mclk; 38 struct clk_mclk_state clk_mclk;
39 struct clk_freq_controllers clk_freq_controllers;
38}; 40};
39 41
40struct clockentry { 42struct clockentry {
@@ -114,5 +116,5 @@ u32 clk_domain_get_f_points(
114); 116);
115int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); 117int clk_get_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
116int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk); 118int clk_set_fll_clks(struct gk20a *g, struct set_fll_clk *fllclk);
117 119int clk_pmu_freq_controller_load(struct gk20a *g, bool bload);
118#endif 120#endif