gpu: nvgpu: set gv10x boot clock

- Set gv10x boot gpcclk to 952 MHz
- Created ops to set gv10x boot gpcclk instead
of using clk arbiter to set clocks

Bug 200399373

Change-Id: Ice5956f79d4a52abf455506a798cf7b914f3d3ed
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1700788
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 10 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk.h b/drivers/gpu/nvgpu/clk/clk.h
index 019a1c11..70b04fc4 100644
--- a/drivers/gpu/nvgpu/clk/clk.h
+++ b/drivers/gpu/nvgpu/clk/clk.h
@@ -35,9 +35,12 @@
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SKIP 0x10
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_MASK 0x1F
 #define NV_PERF_DOMAIN_4X_CLOCK_DOMAIN_SHIFT 0
+#define BOOT_GPCCLK_MHZ 952
 
 struct gk20a;
 
+int clk_set_boot_fll_clk(struct gk20a *g);
+
 /* clock related defines for GPUs supporting clock control from pmu*/
 struct clk_pmupstate {
         struct avfsvinobjs avfs_vinobjs;
@@ -56,6 +59,12 @@ struct clockentry {
                 u32 api_clk_domain;
 };
 
+struct change_fll_clk {
+                u32 api_clk_domain;
+                u16 clkmhz;
+                u32 voltuv;
+};
+
 struct set_fll_clk {
                 u32 voltuv;
                 u16 gpc2clkmhz;
@@ -133,4 +142,5 @@ u32 nvgpu_clk_vf_change_inject_data_fill_gv10x(struct gk20a *g,
 u32 nvgpu_clk_vf_change_inject_data_fill_gp10x(struct gk20a *g,
         struct nv_pmu_clk_rpc *rpccall,
         struct set_fll_clk *setfllclk);
+u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g);
 #endif