diff options
author | Vaikundanathan S <vaikuns@nvidia.com> | 2018-08-28 02:28:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-20 13:50:53 -0400 |
commit | ae809fddbe90bcec0d48e1213fa36cc5ba76550d (patch) | |
tree | bbafc71a543abf4b02e76290d058719f27f5f3b8 /drivers/gpu/nvgpu/clk/clk.c | |
parent | 85c323c3e89d6e1b624b839c3325ae072952e545 (diff) |
gpu:nvgpu: Add GV10x perf event
In case of VFE update, schedule work to set P0 clocks.
Added function nvgpu_clk_set_fll_clk_gv10x to update P0 clocks on perf event.
Fixed MISRA issues caused by this excluding external functions and MACROs
Bug 2331655
Change-Id: Id96c473092ee7f0b651413aefdd4b6f2f59e0b12
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1808014
Reviewed-on: https://git-master.nvidia.com/r/1813881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk.c')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c index f0624595..8532a08b 100644 --- a/drivers/gpu/nvgpu/clk/clk.c +++ b/drivers/gpu/nvgpu/clk/clk.c | |||
@@ -866,6 +866,43 @@ u32 nvgpu_clk_set_boot_fll_clk_gv10x(struct gk20a *g) | |||
866 | return status; | 866 | return status; |
867 | } | 867 | } |
868 | 868 | ||
869 | int nvgpu_clk_set_fll_clk_gv10x(struct gk20a *g) | ||
870 | { | ||
871 | int status; | ||
872 | struct change_fll_clk bootfllclk; | ||
873 | u16 gpcclk_clkmhz = BOOT_GPCCLK_MHZ; | ||
874 | u32 gpcclk_voltuv = 0U; | ||
875 | u32 voltuv = 0U; | ||
876 | |||
877 | status = clk_vf_point_cache(g); | ||
878 | if (status != 0) { | ||
879 | nvgpu_err(g, "caching failed"); | ||
880 | return status; | ||
881 | } | ||
882 | |||
883 | status = clk_domain_get_f_or_v(g, CTRL_CLK_DOMAIN_GPCCLK, | ||
884 | &gpcclk_clkmhz, &gpcclk_voltuv, CTRL_VOLT_DOMAIN_LOGIC); | ||
885 | if (status != 0) { | ||
886 | return status; | ||
887 | } | ||
888 | |||
889 | voltuv = gpcclk_voltuv; | ||
890 | |||
891 | status = volt_set_voltage(g, voltuv, 0U); | ||
892 | if (status != 0) { | ||
893 | nvgpu_err(g, "attempt to set max voltage failed %d", voltuv); | ||
894 | } | ||
895 | |||
896 | bootfllclk.api_clk_domain = CTRL_CLK_DOMAIN_GPCCLK; | ||
897 | bootfllclk.clkmhz = gpcclk_clkmhz; | ||
898 | bootfllclk.voltuv = voltuv; | ||
899 | status = clk_program_fllclks(g, &bootfllclk); | ||
900 | if (status != 0) { | ||
901 | nvgpu_err(g, "attempt to set max gpcclk failed"); | ||
902 | } | ||
903 | return status; | ||
904 | } | ||
905 | |||
869 | u32 clk_domain_get_f_or_v( | 906 | u32 clk_domain_get_f_or_v( |
870 | struct gk20a *g, | 907 | struct gk20a *g, |
871 | u32 clkapidomain, | 908 | u32 clkapidomain, |