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authorVijayakumar Subbu <vsubbu@nvidia.com>2016-07-30 13:44:30 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:49 -0500
commit432017248e432df0619dc2df30f915a52634338f (patch)
tree40bb7a77983fb2753271bc46b346a44ebd6121cf /drivers/gpu/nvgpu/clk/clk.c
parent38ad90b4840434df4650c617a236e1b01f8a43c6 (diff)
gpu: nvgpu: Add dGPU clocks support
JIRA DNVGPU-42 Change-Id: Ic2fca9d0cf82f2823654ac5e8f0772a1eec7b3b5 Signed-off-by: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1205850 (cherry picked from commit b9f5c6bc4e649162d63e33d65b725872340ca114) Reviewed-on: http://git-master/r/1227257 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/clk/clk.c')
-rw-r--r--drivers/gpu/nvgpu/clk/clk.c190
1 files changed, 190 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk.c b/drivers/gpu/nvgpu/clk/clk.c
new file mode 100644
index 00000000..0679efc0
--- /dev/null
+++ b/drivers/gpu/nvgpu/clk/clk.c
@@ -0,0 +1,190 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "clk.h"
16#include "pmuif/gpmuifclk.h"
17#include "pmuif/gpmuifvolt.h"
18#include "ctrl/ctrlclk.h"
19#include "ctrl/ctrlvolt.h"
20#include "gk20a/pmu_gk20a.h"
21
22struct clkrpc_pmucmdhandler_params {
23 struct nv_pmu_clk_rpc *prpccall;
24 u32 success;
25};
26
27static void clkrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
28 void *param, u32 handle, u32 status)
29{
30 struct clkrpc_pmucmdhandler_params *phandlerparams =
31 (struct clkrpc_pmucmdhandler_params *)param;
32
33 gk20a_dbg_info("");
34
35 if (msg->msg.clk.msg_type != NV_PMU_CLK_MSG_ID_RPC) {
36 gk20a_err(dev_from_gk20a(g),
37 "unsupported msg for VFE LOAD RPC %x",
38 msg->msg.clk.msg_type);
39 return;
40 }
41
42 if (phandlerparams->prpccall->b_supported)
43 phandlerparams->success = 1;
44}
45
46u32 clk_pmu_vin_load(struct gk20a *g)
47{
48 struct pmu_cmd cmd;
49 struct pmu_msg msg;
50 struct pmu_payload payload = { {0} };
51 u32 status;
52 u32 seqdesc;
53 struct nv_pmu_clk_rpc rpccall = {0};
54 struct clkrpc_pmucmdhandler_params handler = {0};
55 struct nv_pmu_clk_load *clkload;
56
57 rpccall.function = NV_PMU_CLK_RPC_ID_LOAD;
58 clkload = &rpccall.params.clk_load;
59 clkload->feature = NV_NV_PMU_CLK_LOAD_FEATURE_VIN;
60 clkload->action_mask = NV_NV_PMU_CLK_LOAD_ACTION_MASK_VIN_HW_CAL_PROGRAM_YES << 4;
61
62 cmd.hdr.unit_id = PMU_UNIT_CLK;
63 cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
64 (u32)sizeof(struct pmu_hdr);
65
66 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
67 msg.hdr.size = sizeof(struct pmu_msg);
68
69 payload.in.buf = (u8 *)&rpccall;
70 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
71 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
72 payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
73
74 payload.out.buf = (u8 *)&rpccall;
75 payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
76 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
77 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
78
79 handler.prpccall = &rpccall;
80 handler.success = 0;
81
82 status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
83 PMU_COMMAND_QUEUE_LPQ,
84 clkrpc_pmucmdhandler, (void *)&handler,
85 &seqdesc, ~0);
86
87 if (status) {
88 gk20a_err(dev_from_gk20a(g),
89 "unable to post clk RPC cmd %x",
90 cmd.cmd.clk.cmd_type);
91 goto done;
92 }
93
94 pmu_wait_message_cond(&g->pmu,
95 gk20a_get_gr_idle_timeout(g),
96 &handler.success, 1);
97
98 if (handler.success == 0) {
99 gk20a_err(dev_from_gk20a(g), "rpc call to load vin cal failed");
100 status = -EINVAL;
101 }
102
103done:
104 return status;
105}
106
107u32 clk_pmu_vf_inject(struct gk20a *g)
108{
109 struct pmu_cmd cmd;
110 struct pmu_msg msg;
111 struct pmu_payload payload = { {0} };
112 u32 status;
113 u32 seqdesc;
114 struct nv_pmu_clk_rpc rpccall = {0};
115 struct clkrpc_pmucmdhandler_params handler = {0};
116 struct nv_pmu_clk_vf_change_inject *vfchange;
117
118 rpccall.function = NV_PMU_CLK_RPC_ID_CLK_VF_CHANGE_INJECT;
119 vfchange = &rpccall.params.clk_vf_change_inject;
120 vfchange->flags = 0;
121 vfchange->clk_list.num_domains = 3;
122 vfchange->clk_list.clk_domains[0].clk_domain = CTRL_CLK_DOMAIN_GPC2CLK;
123 vfchange->clk_list.clk_domains[0].clk_freq_khz = 2581 * 1000;
124 vfchange->clk_list.clk_domains[0].clk_flags = 0;
125 vfchange->clk_list.clk_domains[0].current_regime_id =
126 CTRL_CLK_FLL_REGIME_ID_FFR;
127 vfchange->clk_list.clk_domains[0].target_regime_id =
128 CTRL_CLK_FLL_REGIME_ID_FR;
129 vfchange->clk_list.clk_domains[1].clk_domain = CTRL_CLK_DOMAIN_XBAR2CLK;
130 vfchange->clk_list.clk_domains[1].clk_freq_khz = 2505 * 1000;
131 vfchange->clk_list.clk_domains[1].clk_flags = 0;
132 vfchange->clk_list.clk_domains[1].current_regime_id =
133 CTRL_CLK_FLL_REGIME_ID_FFR;
134 vfchange->clk_list.clk_domains[1].target_regime_id =
135 CTRL_CLK_FLL_REGIME_ID_FR;
136 vfchange->clk_list.clk_domains[2].clk_domain = CTRL_CLK_DOMAIN_SYS2CLK;
137 vfchange->clk_list.clk_domains[2].clk_freq_khz = 2328 * 1000;
138 vfchange->clk_list.clk_domains[2].clk_flags = 0;
139 vfchange->clk_list.clk_domains[2].current_regime_id =
140 CTRL_CLK_FLL_REGIME_ID_FFR;
141 vfchange->clk_list.clk_domains[2].target_regime_id =
142 CTRL_CLK_FLL_REGIME_ID_FR;
143 vfchange->volt_list.num_rails = 1;
144 vfchange->volt_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
145 vfchange->volt_list.rails[0].voltage_uv = 825000;
146 vfchange->volt_list.rails[0].voltage_min_noise_unaware_uv = 825000;
147
148 cmd.hdr.unit_id = PMU_UNIT_CLK;
149 cmd.hdr.size = (u32)sizeof(struct nv_pmu_clk_cmd) +
150 (u32)sizeof(struct pmu_hdr);
151
152 cmd.cmd.clk.cmd_type = NV_PMU_CLK_CMD_ID_RPC;
153 msg.hdr.size = sizeof(struct pmu_msg);
154
155 payload.in.buf = (u8 *)&rpccall;
156 payload.in.size = (u32)sizeof(struct nv_pmu_clk_rpc);
157 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
158 payload.in.offset = NV_PMU_CLK_CMD_RPC_ALLOC_OFFSET;
159
160 payload.out.buf = (u8 *)&rpccall;
161 payload.out.size = (u32)sizeof(struct nv_pmu_clk_rpc);
162 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
163 payload.out.offset = NV_PMU_CLK_MSG_RPC_ALLOC_OFFSET;
164
165 handler.prpccall = &rpccall;
166 handler.success = 0;
167
168 status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
169 PMU_COMMAND_QUEUE_LPQ,
170 clkrpc_pmucmdhandler, (void *)&handler,
171 &seqdesc, ~0);
172
173 if (status) {
174 gk20a_err(dev_from_gk20a(g),
175 "unable to post clk RPC cmd %x",
176 cmd.cmd.clk.cmd_type);
177 goto done;
178 }
179
180 pmu_wait_message_cond(&g->pmu,
181 gk20a_get_gr_idle_timeout(g),
182 &handler.success, 1);
183
184 if (handler.success == 0) {
185 gk20a_err(dev_from_gk20a(g), "rpc call to inject clock failed");
186 status = -EINVAL;
187 }
188done:
189 return status;
190}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:29:38 -0400