diff options
author | Sai Nikhil <snikhil@nvidia.com> | 2018-09-11 01:08:54 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-27 02:35:37 -0400 |
commit | c6cfb12d91accc759ed80985573014df89d9cdaa (patch) | |
tree | 0bc9f467e0f52732a9d5916cb804b12b8f00134b /drivers/gpu/nvgpu/boardobj | |
parent | c18c8b5b28b839ac20ae2c4b1003e9b44199016a (diff) |
gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations
MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.
Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.
This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.
JIRA NVGPU-992
Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809757
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/boardobj')
-rw-r--r-- | drivers/gpu/nvgpu/boardobj/boardobjgrp.h | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h index e9df445f..cd13b85e 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h | |||
@@ -234,17 +234,17 @@ struct boardobjgrp { | |||
234 | * be inserted contiguously (i.e. w/o fear of colliding with existing objects). | 234 | * be inserted contiguously (i.e. w/o fear of colliding with existing objects). |
235 | */ | 235 | */ |
236 | #define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp) \ | 236 | #define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp) \ |
237 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 : \ | 237 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \ |
238 | ((((_pboardobjgrp)->objmaxidx + 1) >= (_pboardobjgrp)->objslots) ? \ | 238 | ((((_pboardobjgrp)->objmaxidx + 1U) >= (_pboardobjgrp)->objslots) ? \ |
239 | (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1))) | 239 | (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1U))) |
240 | 240 | ||
241 | /* | 241 | /* |
242 | * Helper macro to determine the number of @ref BOARDOBJ pointers | 242 | * Helper macro to determine the number of @ref BOARDOBJ pointers |
243 | * that are required to be allocated in PMU @ref ppObjects. | 243 | * that are required to be allocated in PMU @ref ppObjects. |
244 | */ | 244 | */ |
245 | #define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp) \ | 245 | #define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp) \ |
246 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 : \ | 246 | ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U : \ |
247 | (u8)((_pboardobjgrp)->objmaxidx + 1)) | 247 | (u8)((_pboardobjgrp)->objmaxidx + 1U)) |
248 | 248 | ||
249 | #define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx) \ | 249 | #define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx) \ |
250 | ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx))) | 250 | ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx))) |
@@ -274,8 +274,8 @@ struct boardobjgrp { | |||
274 | #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \ | 274 | #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask) \ |
275 | { \ | 275 | { \ |
276 | u##mask_width lcl_msk = (u##mask_width)(mask); \ | 276 | u##mask_width lcl_msk = (u##mask_width)(mask); \ |
277 | for (index = 0; lcl_msk != 0; index++, lcl_msk >>= 1) { \ | 277 | for (index = 0; lcl_msk != 0U; index++, lcl_msk >>= 1U) { \ |
278 | if (((u##mask_width)((u64)1) & lcl_msk) == 0) { \ | 278 | if (((u##mask_width)((u64)1) & lcl_msk) == 0U) { \ |
279 | continue; \ | 279 | continue; \ |
280 | } | 280 | } |
281 | 281 | ||
@@ -289,22 +289,22 @@ struct boardobjgrp { | |||
289 | * @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are | 289 | * @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are |
290 | * not supported. | 290 | * not supported. |
291 | */ | 291 | */ |
292 | #define BOARDOBJGRP_UNIT_ID_INVALID 255 | 292 | #define BOARDOBJGRP_UNIT_ID_INVALID 255U |
293 | 293 | ||
294 | /*! | 294 | /*! |
295 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set | 295 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set |
296 | * @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are | 296 | * @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are |
297 | * not supported. | 297 | * not supported. |
298 | */ | 298 | */ |
299 | #define BOARDOBJGRP_GRP_CLASS_ID_INVALID 255 | 299 | #define BOARDOBJGRP_GRP_CLASS_ID_INVALID 255U |
300 | 300 | ||
301 | /*! | 301 | /*! |
302 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set | 302 | * Invalid UNIT_ID. Used to indicate that the implementing class has not set |
303 | * @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces | 303 | * @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces |
304 | * are not supported. | 304 | * are not supported. |
305 | */ | 305 | */ |
306 | #define BOARDOBJGRP_GRP_CMD_ID_INVALID 255 | 306 | #define BOARDOBJGRP_GRP_CMD_ID_INVALID 255U |
307 | #define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID 255 | 307 | #define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID 255U |
308 | 308 | ||
309 | /*! | 309 | /*! |
310 | * Helper macro to construct a BOARDOBJGRP's PMU SW state. | 310 | * Helper macro to construct a BOARDOBJGRP's PMU SW state. |
@@ -379,14 +379,14 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
379 | 379 | ||
380 | #define HIGHESTBITIDX_32(n32) \ | 380 | #define HIGHESTBITIDX_32(n32) \ |
381 | { \ | 381 | { \ |
382 | u32 count = 0; \ | 382 | u32 count = 0U; \ |
383 | while (n32 >>= 1) { \ | 383 | while (n32 >>= 1U) { \ |
384 | count++; \ | 384 | count++; \ |
385 | } \ | 385 | } \ |
386 | n32 = count; \ | 386 | n32 = count; \ |
387 | } | 387 | } |
388 | 388 | ||
389 | #define LOWESTBIT(x) ((x) & (((x)-1) ^ (x))) | 389 | #define LOWESTBIT(x) ((x) & (((x)-1U) ^ (x))) |
390 | 390 | ||
391 | #define HIGHESTBIT(n32) \ | 391 | #define HIGHESTBIT(n32) \ |
392 | { \ | 392 | { \ |
@@ -394,7 +394,7 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
394 | n32 = NVBIT(n32); \ | 394 | n32 = NVBIT(n32); \ |
395 | } | 395 | } |
396 | 396 | ||
397 | #define ONEBITSET(x) ((x) && (((x) & ((x)-1)) == 0)) | 397 | #define ONEBITSET(x) ((x) && (((x) & ((x)-1U)) == 0U)) |
398 | 398 | ||
399 | #define LOWESTBITIDX_32(n32) \ | 399 | #define LOWESTBITIDX_32(n32) \ |
400 | { \ | 400 | { \ |
@@ -404,24 +404,24 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask); | |||
404 | 404 | ||
405 | #define NUMSETBITS_32(n32) \ | 405 | #define NUMSETBITS_32(n32) \ |
406 | { \ | 406 | { \ |
407 | n32 = n32 - ((n32 >> 1) & 0x55555555); \ | 407 | n32 = n32 - ((n32 >> 1U) & 0x55555555U); \ |
408 | n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333); \ | 408 | n32 = (n32 & 0x33333333U) + ((n32 >> 2U) & 0x33333333U); \ |
409 | n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24; \ | 409 | n32 = (((n32 + (n32 >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U; \ |
410 | } | 410 | } |
411 | 411 | ||
412 | #define IDX_32(n32) \ | 412 | #define IDX_32(n32) \ |
413 | { \ | 413 | { \ |
414 | u32 idx = 0; \ | 414 | u32 idx = 0U; \ |
415 | if ((n32) & 0xFFFF0000) \ | 415 | if ((n32) & 0xFFFF0000U) \ |
416 | idx += 16; \ | 416 | idx += 16U; \ |
417 | if ((n32) & 0xFF00FF00) \ | 417 | if ((n32) & 0xFF00FF00U) \ |
418 | idx += 8; \ | 418 | idx += 8U; \ |
419 | if ((n32) & 0xF0F0F0F0) \ | 419 | if ((n32) & 0xF0F0F0F0U) \ |
420 | idx += 4; \ | 420 | idx += 4U; \ |
421 | if ((n32) & 0xCCCCCCCC) \ | 421 | if ((n32) & 0xCCCCCCCCU) \ |
422 | idx += 2; \ | 422 | idx += 2U; \ |
423 | if ((n32) & 0xAAAAAAAA) \ | 423 | if ((n32) & 0xAAAAAAAAU) \ |
424 | idx += 1; \ | 424 | idx += 1U; \ |
425 | (n32) = idx; \ | 425 | (n32) = idx; \ |
426 | } | 426 | } |
427 | 427 | ||