summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
diff options
context:
space:
mode:
authorSrirangan <smadhavan@nvidia.com>2018-08-28 01:39:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-28 09:47:36 -0400
commit361eca66b58051d46daad1b600eef1f72b7f15c0 (patch)
treee101ab419710c0ceb3b641098210d4147c11919e /drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
parent4032e8915a65aa94f8b556676c5606683ec28f52 (diff)
gpu: nvgpu: boardobj: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I604d85367cd4b99c39df2b9fa2d7a7219ef941d5 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807153 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c')
-rw-r--r--drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
index 6d4b4520..60e5caf6 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e32.c
@@ -38,8 +38,9 @@ u32 boardobjgrpconstruct_e32(struct gk20a *g,
38 objslots = 32; 38 objslots = 32;
39 39
40 status = boardobjgrpmask_e32_init(&pboardobjgrp_e32->mask, NULL); 40 status = boardobjgrpmask_e32_init(&pboardobjgrp_e32->mask, NULL);
41 if (status) 41 if (status) {
42 goto boardobjgrpconstruct_e32_exit; 42 goto boardobjgrpconstruct_e32_exit;
43 }
43 44
44 pboardobjgrp_e32->super.type = CTRL_BOARDOBJGRP_TYPE_E32; 45 pboardobjgrp_e32->super.type = CTRL_BOARDOBJGRP_TYPE_E32;
45 pboardobjgrp_e32->super.ppobjects = pboardobjgrp_e32->objects; 46 pboardobjgrp_e32->super.ppobjects = pboardobjgrp_e32->objects;
@@ -47,8 +48,9 @@ u32 boardobjgrpconstruct_e32(struct gk20a *g,
47 pboardobjgrp_e32->super.mask = &(pboardobjgrp_e32->mask.super); 48 pboardobjgrp_e32->super.mask = &(pboardobjgrp_e32->mask.super);
48 49
49 status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super); 50 status = boardobjgrp_construct_super(g, &pboardobjgrp_e32->super);
50 if (status) 51 if (status) {
51 goto boardobjgrpconstruct_e32_exit; 52 goto boardobjgrpconstruct_e32_exit;
53 }
52 54
53 pboardobjgrp_e32->super.pmuhdrdatainit = boardobjgrp_pmuhdrdatainit_e32; 55 pboardobjgrp_e32->super.pmuhdrdatainit = boardobjgrp_pmuhdrdatainit_e32;
54 56
@@ -67,11 +69,13 @@ u32 boardobjgrp_pmuhdrdatainit_e32(struct gk20a *g,
67 69
68 nvgpu_log_info(g, " "); 70 nvgpu_log_info(g, " ");
69 71
70 if (pboardobjgrp == NULL) 72 if (pboardobjgrp == NULL) {
71 return -EINVAL; 73 return -EINVAL;
74 }
72 75
73 if (pboardobjgrppmu == NULL) 76 if (pboardobjgrppmu == NULL) {
74 return -EINVAL; 77 return -EINVAL;
78 }
75 status = boardobjgrpmask_export(mask, 79 status = boardobjgrpmask_export(mask,
76 mask->bitcount, 80 mask->bitcount,
77 &pgrpe32->obj_mask.super); 81 &pgrpe32->obj_mask.super);