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author | Philip Elcan <pelcan@nvidia.com> | 2018-08-29 15:46:12 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-07 00:33:50 -0400 |
commit | 7f8226887c28267d3c2351692d4429ead1e17695 (patch) | |
tree | aa09c45e496b058044c9d9a94c94d9922c572285 /drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c | |
parent | 0e58ebaae13dd59b6aba5297f898e7c89fcd2742 (diff) |
gpu: nvgpu: cleanup return types for MISRA 10.3
This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.
JIRA NVGPU-647
Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c')
-rw-r--r-- | drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c index a7da8064..b26f8ecb 100644 --- a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c +++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c | |||
@@ -27,10 +27,10 @@ | |||
27 | #include "boardobjgrp.h" | 27 | #include "boardobjgrp.h" |
28 | #include "boardobjgrpmask.h" | 28 | #include "boardobjgrpmask.h" |
29 | 29 | ||
30 | u32 boardobjgrpconstruct_e255(struct gk20a *g, | 30 | int boardobjgrpconstruct_e255(struct gk20a *g, |
31 | struct boardobjgrp_e255 *pboardobjgrp_e255) | 31 | struct boardobjgrp_e255 *pboardobjgrp_e255) |
32 | { | 32 | { |
33 | u32 status = 0; | 33 | int status = 0; |
34 | u8 objslots; | 34 | u8 objslots; |
35 | 35 | ||
36 | nvgpu_log_info(g, " "); | 36 | nvgpu_log_info(g, " "); |
@@ -58,14 +58,14 @@ boardobjgrpconstruct_e255_exit: | |||
58 | return status; | 58 | return status; |
59 | } | 59 | } |
60 | 60 | ||
61 | u32 boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g, | 61 | int boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g, |
62 | struct boardobjgrp *pboardobjgrp, | 62 | struct boardobjgrp *pboardobjgrp, |
63 | struct nv_pmu_boardobjgrp_super *pboardobjgrppmu, | 63 | struct nv_pmu_boardobjgrp_super *pboardobjgrppmu, |
64 | struct boardobjgrpmask *mask) | 64 | struct boardobjgrpmask *mask) |
65 | { | 65 | { |
66 | struct nv_pmu_boardobjgrp_e255 *pgrpe255 = | 66 | struct nv_pmu_boardobjgrp_e255 *pgrpe255 = |
67 | (struct nv_pmu_boardobjgrp_e255 *)pboardobjgrppmu; | 67 | (struct nv_pmu_boardobjgrp_e255 *)pboardobjgrppmu; |
68 | u32 status; | 68 | int status; |
69 | 69 | ||
70 | nvgpu_log_info(g, " "); | 70 | nvgpu_log_info(g, " "); |
71 | 71 | ||