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authorSrirangan <smadhavan@nvidia.com>2018-08-28 01:39:19 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-28 09:47:36 -0400
commit361eca66b58051d46daad1b600eef1f72b7f15c0 (patch)
treee101ab419710c0ceb3b641098210d4147c11919e /drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
parent4032e8915a65aa94f8b556676c5606683ec28f52 (diff)
gpu: nvgpu: boardobj: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I604d85367cd4b99c39df2b9fa2d7a7219ef941d5 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1807153 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c')
-rw-r--r--drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c12
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
index 1f2cd836..a7da8064 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp_e255.c
@@ -37,8 +37,9 @@ u32 boardobjgrpconstruct_e255(struct gk20a *g,
37 37
38 objslots = 255; 38 objslots = 255;
39 status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL); 39 status = boardobjgrpmask_e255_init(&pboardobjgrp_e255->mask, NULL);
40 if (status) 40 if (status) {
41 goto boardobjgrpconstruct_e255_exit; 41 goto boardobjgrpconstruct_e255_exit;
42 }
42 43
43 pboardobjgrp_e255->super.type = CTRL_BOARDOBJGRP_TYPE_E255; 44 pboardobjgrp_e255->super.type = CTRL_BOARDOBJGRP_TYPE_E255;
44 pboardobjgrp_e255->super.ppobjects = pboardobjgrp_e255->objects; 45 pboardobjgrp_e255->super.ppobjects = pboardobjgrp_e255->objects;
@@ -46,8 +47,9 @@ u32 boardobjgrpconstruct_e255(struct gk20a *g,
46 pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super); 47 pboardobjgrp_e255->super.mask = &(pboardobjgrp_e255->mask.super);
47 48
48 status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super); 49 status = boardobjgrp_construct_super(g, &pboardobjgrp_e255->super);
49 if (status) 50 if (status) {
50 goto boardobjgrpconstruct_e255_exit; 51 goto boardobjgrpconstruct_e255_exit;
52 }
51 53
52 pboardobjgrp_e255->super.pmuhdrdatainit = 54 pboardobjgrp_e255->super.pmuhdrdatainit =
53 boardobjgrp_pmuhdrdatainit_e255; 55 boardobjgrp_pmuhdrdatainit_e255;
@@ -67,11 +69,13 @@ u32 boardobjgrp_pmuhdrdatainit_e255(struct gk20a *g,
67 69
68 nvgpu_log_info(g, " "); 70 nvgpu_log_info(g, " ");
69 71
70 if (pboardobjgrp == NULL) 72 if (pboardobjgrp == NULL) {
71 return -EINVAL; 73 return -EINVAL;
74 }
72 75
73 if (pboardobjgrppmu == NULL) 76 if (pboardobjgrppmu == NULL) {
74 return -EINVAL; 77 return -EINVAL;
78 }
75 79
76 status = boardobjgrpmask_export(mask, 80 status = boardobjgrpmask_export(mask,
77 mask->bitcount, 81 mask->bitcount,