diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-11-09 17:13:25 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-22 03:59:28 -0500 |
commit | 8fe633449f92d35b60a60de647a4e8fc1b5c8936 (patch) | |
tree | f29ee0ed1c9eba66b99033a17d3b2854662b0a15 /drivers/gpu/nvgpu/Makefile | |
parent | f34a4d0b125ebf45373e40478925b3eb75b7898a (diff) |
gpu: nvgpu: Add check_priv_security fuse ops
-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
during hal initialization
-For igpu non simulation platforms, fuses are read
to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
in LS mode and this needs wpr_enabled set to 1
AND vpr_auto_fetch_disable set to 0. In this case
gmmu tries to pull wpr and vpr settings from tegra mc
Bug 2018223
Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/Makefile')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 72946fc0..a4ef22e5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -114,6 +114,7 @@ nvgpu-y := \ | |||
114 | gm20b/mm_gm20b.o \ | 114 | gm20b/mm_gm20b.o \ |
115 | gm20b/regops_gm20b.o \ | 115 | gm20b/regops_gm20b.o \ |
116 | gm20b/therm_gm20b.o \ | 116 | gm20b/therm_gm20b.o \ |
117 | gm20b/fuse_gm20b.o \ | ||
117 | boardobj/boardobj.o \ | 118 | boardobj/boardobj.o \ |
118 | boardobj/boardobjgrp.o \ | 119 | boardobj/boardobjgrp.o \ |
119 | boardobj/boardobjgrpmask.o \ | 120 | boardobj/boardobjgrpmask.o \ |
@@ -166,6 +167,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
166 | common/linux/vgpu/css_vgpu.o \ | 167 | common/linux/vgpu/css_vgpu.o \ |
167 | common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \ | 168 | common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \ |
168 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ | 169 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ |
170 | common/linux/vgpu/gm20b/vgpu_fuse_gm20b.o \ | ||
169 | common/linux/vgpu/sysfs_vgpu.o | 171 | common/linux/vgpu/sysfs_vgpu.o |
170 | 172 | ||
171 | nvgpu-$(CONFIG_COMMON_CLK) += \ | 173 | nvgpu-$(CONFIG_COMMON_CLK) += \ |
@@ -195,6 +197,7 @@ nvgpu-y += \ | |||
195 | gp10b/fecs_trace_gp10b.o \ | 197 | gp10b/fecs_trace_gp10b.o \ |
196 | gp10b/priv_ring_gp10b.o \ | 198 | gp10b/priv_ring_gp10b.o \ |
197 | gp10b/gp10b.o \ | 199 | gp10b/gp10b.o \ |
200 | gp10b/fuse_gp10b.o \ | ||
198 | gp106/hal_gp106.o \ | 201 | gp106/hal_gp106.o \ |
199 | gp106/mm_gp106.o \ | 202 | gp106/mm_gp106.o \ |
200 | gp106/flcn_gp106.o \ | 203 | gp106/flcn_gp106.o \ |
@@ -208,6 +211,7 @@ nvgpu-y += \ | |||
208 | gp106/fb_gp106.o \ | 211 | gp106/fb_gp106.o \ |
209 | gp106/regops_gp106.o \ | 212 | gp106/regops_gp106.o \ |
210 | gp106/bios_gp106.o \ | 213 | gp106/bios_gp106.o \ |
214 | gp106/fuse_gp106.o \ | ||
211 | pstate/pstate.o \ | 215 | pstate/pstate.o \ |
212 | clk/clk_vin.o \ | 216 | clk/clk_vin.o \ |
213 | clk/clk_fll.o \ | 217 | clk/clk_fll.o \ |
@@ -247,6 +251,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o | |||
247 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | 251 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ |
248 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ | 252 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ |
249 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ | 253 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ |
254 | common/linux/vgpu/gp10b/vgpu_fuse_gp10b.o \ | ||
250 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o | 255 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o |
251 | 256 | ||
252 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) | 257 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) |