gpu: nvgpu: Add fifo conf support for gp10x

Added fifo configuration support for gp104 and
gp106. These GPU chips have more number of
channel fifo and runlist than gp10b.
Added get_num_fifos and
eng_runlist_base_size function pointer
to find out the actual value from HW headers.

JIRA DNVGPU-25

Change-Id: I2322a6354eaa2af2b2605f3e9eedebf9827c7dda
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1164653
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 1579e6eb..643c0967 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -25,7 +25,8 @@ nvgpu-y += \
         $(nvgpu-t18x)/gp106/gr_gp106.o \
         $(nvgpu-t18x)/gp106/gr_ctx_gp106.o \
         $(nvgpu-t18x)/gp106/acr_gp106.o \
-        $(nvgpu-t18x)/gp106/sec2_gp106.o
+        $(nvgpu-t18x)/gp106/sec2_gp106.o \
+        $(nvgpu-t18x)/gp106/fifo_gp106.o
 
 nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o