gpu: nvgpu: Introduce priv ring HAL and define ISR

Introduce a priv ring HAL and define ISR as the only function in it.
Introduce a gp10b version of the ISR that writes error message to
UART for every priv ring error, and leave the old chips with silent
error handling.

Bug 1846641

Change-Id: I73e38396205ac7bb7b8488b7fbca3ff67a3db3bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1473696
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 59c81826..411e06cc 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -165,6 +165,7 @@ nvgpu-y += \
         gp10b/therm_gp10b.o \
         gp10b/fecs_trace_gp10b.o \
         gp10b/gp10b_sysfs.o \
+        gp10b/priv_ring_gp10b.o \
         gp10b/gp10b.o \
         gp106/hal_gp106.o \
         gp106/mm_gp106.o \