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authorAlex Frid <afrid@nvidia.com>2014-09-24 00:37:36 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:28 -0400
commitad39ba2b9e514f99dca588bad799ce63ac8022be (patch)
tree46937dc810f471c4d06f66ddc7555390a338b130 /drivers/gpu/nvgpu/Kconfig
parent3a81ed7e979343df35d65279fb101cbb5f0ccfc7 (diff)
gpu: nvgpu: Add option to enable GPCPLL NA mode
Added configuration option to enable GM20b GPCPLL noise aware (NA) mode. In this mode PLL output frequency is automatically adjusted when GM20b voltage is fluctuating. NA mode is disabled by default. Bug 1555318 Change-Id: Ia9741fd02ddacaf4743e5397b729293fa5181f84 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/534079 Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/Kconfig')
-rw-r--r--drivers/gpu/nvgpu/Kconfig9
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/Kconfig b/drivers/gpu/nvgpu/Kconfig
index 1ea9e060..88c3130d 100644
--- a/drivers/gpu/nvgpu/Kconfig
+++ b/drivers/gpu/nvgpu/Kconfig
@@ -79,3 +79,12 @@ config TEGRA_ACR
79 Enable Support for Loading High Secure binary, and using 79 Enable Support for Loading High Secure binary, and using
80 Write Protected Regions (WPR) for storing ucodes, and bootstrap 80 Write Protected Regions (WPR) for storing ucodes, and bootstrap
81 PMU, FECS and GPCCS in Low Secure mode. 81 PMU, FECS and GPCCS in Low Secure mode.
82
83config TEGRA_USE_NA_GPCPLL
84 bool "Enable noise aware mode of GM20B GPCPLL on Tegra"
85 depends on TEGRA_CLK_FRAMEWORK
86 default n
87 help
88 Enable noise aware (NA) mode of GM20b GPCPLL. In this mode PLL output
89 frequency is automatically adjusted when GM20b voltage is fluctuating
90 because of transient PMIC or power distribution tree noise.