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author | Scott Long <scottl@nvidia.com> | 2018-07-09 13:32:25 -0400 |
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committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-07-30 22:55:13 -0400 |
commit | d9956443820d64ac7f6e2fe7a9d10c1ac4956938 (patch) | |
tree | b5fc701d815ccf9cebc2a093e16feeea48bbc4c9 /Makefile.umbrella.tmk | |
parent | 82a90170d3ecbed5106409546f33afa5eaea3ddf (diff) |
gpu: nvgpu: fix MISRA Rule 11.6 issue with fence pool mgmt
MISRA Rule 11.6 prohibits the casting of an integer value to a
void *.
The nvgpu allocator used for the fence pool stores the base
address of the associated memory as a u64 and returns it via
nvgpu_alloc_base().
In gk20a_free_fence_pool() this u64 value was cast to a void *
before being passed to nvgpu_vfree() (leading to the violation).
This change modifies gk20a_free_fence_pool() to cast the base
address back to the original struct gk20a_fence * to eliminate
the violation.
JIRA NVGPU-895: MISRA Rule 11.6 violations
Change-Id: If89cf2c1bc8ea4b0b59da4cf8b1c167738f6badc
Signed-off-by: Scott Long <scottl@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1774530
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'Makefile.umbrella.tmk')
0 files changed, 0 insertions, 0 deletions