gpu: nvgpu: move gp106 clk debugfs to linux

Move linux dependencies and CONFIG_DEBUG_FS to linux specific
code from common driver for gp106 clk debugfs. There is no
code change in functions moved from gp106/clk_gp106.c.

It uses nvgpu_os_linux_ops to add gp106 specific clk debugfs
ops. The linux specific part of nvgpu driver uses this op
to initialize gp106 clk debugfs.

As gv100 also uses gp106 clk debugfs ops, set up os ops for
gv100.

JIRA NVGPU-603

Change-Id: Ib55ef051b13366e5907e1d05376bb18bf42c8653
Signed-off-by: Nitin Kumbhar <nkumbhar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797904
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

16 files changed, 404 insertions, 206 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index e74fa2bb..24322f82 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -51,6 +51,8 @@ nvgpu-y += \
         os/linux/os_ops.o \
         os/linux/os_ops_gm20b.o \
         os/linux/os_ops_gp10b.o \
+        os/linux/os_ops_gp106.o \
+        os/linux/os_ops_gv100.o \
         os/linux/kmem.o \
         os/linux/timers.o \
         os/linux/ioctl.o \
@@ -98,6 +100,7 @@ nvgpu-$(CONFIG_DEBUG_FS) += \
         os/linux/debug_allocator.o \
         os/linux/debug_hal.o \
         os/linux/debug_clk_gm20b.o \
+        os/linux/debug_clk_gp106.o \
         os/linux/debug_bios.o \
         os/linux/debug_ltc.o \
         os/linux/debug_xve.o
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f0b0bebe..be00f708 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1089,6 +1089,7 @@ struct gpu_ops {
                         u32 clkapidomain, u32 *pfpointscount,
                         u16 *pfreqpointsinmhz);
                 unsigned long (*measure_freq)(struct gk20a *g, u32 api_domain);
+                u32 (*get_rate_cntr)(struct gk20a *g, struct namemap_cfg *c);
                 unsigned long (*get_rate)(struct gk20a *g, u32 api_domain);
                 int (*set_rate)(struct gk20a *g, u32 api_domain, unsigned long rate);
                 unsigned long (*get_fmax_at_vmin_safe)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c
index dd7a2dd6..13a401f0 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c
@@ -22,11 +22,6 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifdef CONFIG_DEBUG_FS
-#include <linux/debugfs.h>
-#include "os/linux/os_linux.h"
-#endif
-
 #include <nvgpu/kmem.h>
 #include <nvgpu/io.h>
 #include <nvgpu/list.h>
@@ -42,15 +37,9 @@
 
 #include <nvgpu/hw/gp106/hw_trim_gp106.h>
 
-#ifdef CONFIG_DEBUG_FS
-static int clk_gp106_debugfs_init(struct gk20a *g);
-#endif
-
 #define NUM_NAMEMAPS    4
 #define XTAL4X_KHZ 108000
 
-
-static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *);
 u32 gp106_crystal_clk_hz(struct gk20a *g)
 {
         return (XTAL4X_KHZ * 1000);
@@ -173,16 +162,11 @@ int gp106_init_clk_support(struct gk20a *g)
 
         clk->g = g;
 
-#ifdef CONFIG_DEBUG_FS
-        if (!clk->debugfs_set) {
-                if (!clk_gp106_debugfs_init(g))
-                        clk->debugfs_set = true;
-        }
-#endif
         return err;
 }
 
-static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) {
+u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c)
+{
         u32 save_reg;
         u32 retries;
         u32 cntr = 0;
@@ -275,174 +259,6 @@ int gp106_clk_domain_get_f_points(
         return status;
 }
 
-
-#ifdef CONFIG_DEBUG_FS
-static int gp106_get_rate_show(void *data , u64 *val) {
-        struct namemap_cfg *c = (struct namemap_cfg *) data;
-        struct gk20a *g = c->g;
-
-        *val = c->is_counter ? (u64)c->scale * gp106_get_rate_cntr(g, c) :
-                0 /* TODO PLL read */;
-        return 0;
-}
-DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
-
-static int sys_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int sys_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
-
-static int ltc_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int ltc_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
-
-static int xbar_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int xbar_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
-                        xbar_cfc_write, "%llu\n");
-
-static int gpc_cfc_read(void *data , u64 *val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        bool bload = boardobjgrpmask_bitget(
-                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
-                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-
-        /* val = 1 implies CLFC is loaded or enabled */
-        *val = bload ? 1 : 0;
-        return 0;
-}
-static int gpc_cfc_write(void *data , u64 val)
-{
-        struct gk20a *g = (struct gk20a *)data;
-        int status;
-        /* val = 1 implies load or enable the CLFC */
-        bool bload = val ? true : false;
-
-        nvgpu_clk_arb_pstate_change_lock(g, true);
-        status = clk_pmu_freq_controller_load(g, bload,
-                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
-        nvgpu_clk_arb_pstate_change_lock(g, false);
-
-        return status;
-}
-DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
-
-static int clk_gp106_debugfs_init(struct gk20a *g)
-{
-        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
-        struct dentry *gpu_root = l->debugfs;
-        struct dentry *clocks_root, *clk_freq_ctlr_root;
-        struct dentry *d;
-        unsigned int i;
-
-        if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
-                return -ENOMEM;
-
-        clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
-        if (clk_freq_ctlr_root == NULL)
-                return -ENOMEM;
-
-        d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &sys_cfc_fops);
-        d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &ltc_cfc_fops);
-        d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &xbar_cfc_fops);
-        d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
-                                g, &gpc_cfc_fops);
-
-        nvgpu_log(g, gpu_dbg_info, "g=%p", g);
-
-        for (i = 0; i < g->clk.namemap_num; i++) {
-                if (g->clk.clk_namemap[i].is_enable) {
-                        d = debugfs_create_file(
-                                g->clk.clk_namemap[i].name,
-                                S_IRUGO,
-                                clocks_root,
-                                &g->clk.clk_namemap[i],
-                                &get_rate_fops);
-                        if (!d)
-                                goto err_out;
-                }
-        }
-        return 0;
-
-err_out:
-        pr_err("%s: Failed to make debugfs node\n", __func__);
-        debugfs_remove_recursive(clocks_root);
-        return -ENOMEM;
-}
-#endif /* CONFIG_DEBUG_FS */
-
 int gp106_suspend_clk_support(struct gk20a *g)
 {
         nvgpu_mutex_destroy(&g->clk.clk_mutex);
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h
index b7ab3164..079b94f0 100644
--- a/drivers/gpu/nvgpu/gp106/clk_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h
@@ -23,6 +23,7 @@
 #define CLK_GP106_H
 
 #include <nvgpu/lock.h>
+#include <nvgpu/clk.h>
 
 #define CLK_NAMEMAP_INDEX_GPC2CLK       0x00
 #define CLK_NAMEMAP_INDEX_XBAR2CLK      0x02
@@ -36,22 +37,7 @@
 #define XTAL_CNTR_DELAY         1000    /* we need acuracy up to the ms   */
 #define XTAL_SCALE_TO_KHZ       1
 
-
-
-struct namemap_cfg {
-        u32 namemap;
-        u32 is_enable;  /* Namemap enabled */
-        u32 is_counter; /* Using cntr */
-        struct gk20a *g;
-        struct {
-                u32 reg_ctrl_addr;
-                u32 reg_ctrl_idx;
-                u32 reg_cntr_addr;
-        } cntr;
-        u32 scale;
-        char name[24];
-};
-
+u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c);
 int gp106_init_clk_support(struct gk20a *g);
 u32 gp106_crystal_clk_hz(struct gk20a *g);
 unsigned long gp106_clk_measure_freq(struct gk20a *g, u32 api_domain);
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index f1a701a0..af2d4c00 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -673,6 +673,7 @@ static const struct gpu_ops gp106_ops = {
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
                 .get_crystal_clk_hz = gp106_crystal_clk_hz,
+                .get_rate_cntr = gp106_get_rate_cntr,
                 .measure_freq = gp106_clk_measure_freq,
                 .suspend_clk_support = gp106_suspend_clk_support,
                 .clk_domain_get_f_points = gp106_clk_domain_get_f_points,
@@ -848,6 +849,7 @@ int gp106_init_hal(struct gk20a *g)
          */
         gops->clk.init_clk_support = gp106_ops.clk.init_clk_support;
         gops->clk.get_crystal_clk_hz = gp106_ops.clk.get_crystal_clk_hz;
+        gops->clk.get_rate_cntr = gp106_ops.clk.get_rate_cntr;
         gops->clk.measure_freq = gp106_ops.clk.measure_freq;
         gops->clk.suspend_clk_support = gp106_ops.clk.suspend_clk_support;
         gops->clk.mclk_init = gp106_ops.clk.mclk_init;
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 295e896d..78798196 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -769,6 +769,7 @@ static const struct gpu_ops gv100_ops = {
         .clk = {
                 .init_clk_support = gp106_init_clk_support,
                 .get_crystal_clk_hz = gp106_crystal_clk_hz,
+                .get_rate_cntr = gp106_get_rate_cntr,
                 .measure_freq = gp106_clk_measure_freq,
                 .suspend_clk_support = gp106_suspend_clk_support,
         },
@@ -976,6 +977,7 @@ int gv100_init_hal(struct gk20a *g)
 
         /* clocks */
         gops->clk.init_clk_support = gv100_ops.clk.init_clk_support;
+        gops->clk.get_rate_cntr = gv100_ops.clk.get_rate_cntr;
         gops->clk.get_crystal_clk_hz = gv100_ops.clk.get_crystal_clk_hz;
         gops->clk.measure_freq = gv100_ops.clk.measure_freq;
         gops->clk.suspend_clk_support = gv100_ops.clk.suspend_clk_support;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk.h b/drivers/gpu/nvgpu/include/nvgpu/clk.h
new file mode 100644
index 00000000..62bb0f94
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/clk.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __NVGPU_CLK_H__
+#define __NVGPU_CLK_H__
+
+#define CLK_NAME_MAX    24
+
+struct namemap_cfg {
+        u32 namemap;
+        u32 is_enable;  /* Namemap enabled */
+        u32 is_counter; /* Using cntr */
+        struct gk20a *g;
+        struct {
+                u32 reg_ctrl_addr;
+                u32 reg_ctrl_idx;
+                u32 reg_cntr_addr;
+        } cntr;
+        u32 scale;
+        char name[CLK_NAME_MAX];
+};
+
+#endif
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.c b/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.c
new file mode 100644
index 00000000..4900c005
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/debugfs.h>
+
+#include <nvgpu/clk.h>
+
+#include "os_linux.h"
+
+void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock);
+
+static int gp106_get_rate_show(void *data , u64 *val)
+{
+        struct namemap_cfg *c = (struct namemap_cfg *)data;
+        struct gk20a *g = c->g;
+
+        if (!g->ops.clk.get_rate_cntr)
+                return -EINVAL;
+
+        *val = c->is_counter ? (u64)c->scale * g->ops.clk.get_rate_cntr(g, c) :
+                0 /* TODO PLL read */;
+
+        return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n");
+
+static int sys_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int sys_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_SYS);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(sys_cfc_fops, sys_cfc_read, sys_cfc_write, "%llu\n");
+
+static int ltc_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int ltc_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_LTC);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(ltc_cfc_fops, ltc_cfc_read, ltc_cfc_write, "%llu\n");
+
+static int xbar_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int xbar_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_XBAR);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(xbar_cfc_fops, xbar_cfc_read,
+                        xbar_cfc_write, "%llu\n");
+
+static int gpc_cfc_read(void *data , u64 *val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        bool bload = boardobjgrpmask_bitget(
+                &g->clk_pmu.clk_freq_controllers.freq_ctrl_load_mask.super,
+                CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
+
+        /* val = 1 implies CLFC is loaded or enabled */
+        *val = bload ? 1 : 0;
+        return 0;
+}
+static int gpc_cfc_write(void *data , u64 val)
+{
+        struct gk20a *g = (struct gk20a *)data;
+        int status;
+        /* val = 1 implies load or enable the CLFC */
+        bool bload = val ? true : false;
+
+        nvgpu_clk_arb_pstate_change_lock(g, true);
+        status = clk_pmu_freq_controller_load(g, bload,
+                        CTRL_CLK_CLK_FREQ_CONTROLLER_ID_GPC0);
+        nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+DEFINE_SIMPLE_ATTRIBUTE(gpc_cfc_fops, gpc_cfc_read, gpc_cfc_write, "%llu\n");
+
+int gp106_clk_init_debugfs(struct gk20a *g)
+{
+        struct nvgpu_os_linux *l = nvgpu_os_linux_from_gk20a(g);
+        struct dentry *gpu_root = l->debugfs;
+        struct dentry *clocks_root, *clk_freq_ctlr_root;
+        struct dentry *d;
+        unsigned int i;
+
+        if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root)))
+                return -ENOMEM;
+
+        clk_freq_ctlr_root = debugfs_create_dir("clk_freq_ctlr", gpu_root);
+        if (clk_freq_ctlr_root == NULL)
+                return -ENOMEM;
+
+        d = debugfs_create_file("sys", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &sys_cfc_fops);
+        d = debugfs_create_file("ltc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &ltc_cfc_fops);
+        d = debugfs_create_file("xbar", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &xbar_cfc_fops);
+        d = debugfs_create_file("gpc", S_IRUGO | S_IWUSR, clk_freq_ctlr_root,
+                                g, &gpc_cfc_fops);
+
+        nvgpu_log(g, gpu_dbg_info, "g=%p", g);
+
+        for (i = 0; i < g->clk.namemap_num; i++) {
+                if (g->clk.clk_namemap[i].is_enable) {
+                        d = debugfs_create_file(
+                                g->clk.clk_namemap[i].name,
+                                S_IRUGO,
+                                clocks_root,
+                                &g->clk.clk_namemap[i],
+                                &get_rate_fops);
+                        if (!d)
+                                goto err_out;
+                }
+        }
+        return 0;
+
+err_out:
+        pr_err("%s: Failed to make debugfs node\n", __func__);
+        debugfs_remove_recursive(clocks_root);
+        return -ENOMEM;
+}
diff --git a/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.h b/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.h
new file mode 100644
index 00000000..b1d031d9
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/debug_clk_gp106.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __DEBUG_CLK_GP106_H
+#define __DEBUG_CLK_GP106_H
+
+#ifdef CONFIG_DEBUG_FS
+int gp106_clk_init_debugfs(struct gk20a *g);
+#else
+inline int gp106_clk_init_debugfs(struct gk20a *g)
+{
+        return 0;
+}
+#endif
+
+#endif
diff --git a/drivers/gpu/nvgpu/os/linux/module.c b/drivers/gpu/nvgpu/os/linux/module.c
index d226ceeb..02b0ea5c 100644
--- a/drivers/gpu/nvgpu/os/linux/module.c
+++ b/drivers/gpu/nvgpu/os/linux/module.c
@@ -198,6 +198,14 @@ int nvgpu_finalize_poweron_linux(struct nvgpu_os_linux *l)
                 return err;
         }
 
+        if (l->ops.clk.init_debugfs) {
+                err = l->ops.clk.init_debugfs(g);
+                if (err) {
+                        nvgpu_err(g, "failed to init linux clk debugfs");
+                        return err;
+                }
+        }
+
         l->init_done = true;
 
         return 0;
@@ -250,6 +258,10 @@ int gk20a_pm_finalize_poweron(struct device *dev)
         if (err)
                 goto done;
 
+        err = nvgpu_init_os_linux_ops(l);
+        if (err)
+                goto done;
+
         err = nvgpu_finalize_poweron_linux(l);
         if (err)
                 goto done;
@@ -268,10 +280,6 @@ int gk20a_pm_finalize_poweron(struct device *dev)
 
         trace_gk20a_finalize_poweron_done(dev_name(dev));
 
-        err = nvgpu_init_os_linux_ops(l);
-        if (err)
-                goto done;
-
         enable_irq(g->irq_stall);
         if (g->irq_stall != g->irq_nonstall)
                 enable_irq(g->irq_nonstall);
diff --git a/drivers/gpu/nvgpu/os/linux/os_linux.h b/drivers/gpu/nvgpu/os/linux/os_linux.h
index 5f35db09..96eff12e 100644
--- a/drivers/gpu/nvgpu/os/linux/os_linux.h
+++ b/drivers/gpu/nvgpu/os/linux/os_linux.h
@@ -38,6 +38,10 @@ struct nvgpu_os_linux_ops {
                                                void *scatter_buffer_ptr,
                                                size_t scatter_buffer_size);
         } cde;
+
+        struct {
+                int (*init_debugfs)(struct gk20a *g);
+        } clk;
 };
 
 struct nvgpu_os_linux {
diff --git a/drivers/gpu/nvgpu/os/linux/os_ops.c b/drivers/gpu/nvgpu/os/linux/os_ops.c
index 14f92787..5fc5beb4 100644
--- a/drivers/gpu/nvgpu/os/linux/os_ops.c
+++ b/drivers/gpu/nvgpu/os/linux/os_ops.c
@@ -18,6 +18,8 @@
 
 #include "os_ops_gm20b.h"
 #include "os_ops_gp10b.h"
+#include "os_ops_gp106.h"
+#include "os_ops_gv100.h"
 
 int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
 {
@@ -32,6 +34,12 @@ int nvgpu_init_os_linux_ops(struct nvgpu_os_linux *l)
         case NVGPU_GPUID_GP10B:
                 nvgpu_gp10b_init_os_ops(l);
                 break;
+        case NVGPU_GPUID_GP106:
+                nvgpu_gp106_init_os_ops(l);
+                break;
+        case NVGPU_GPUID_GV100:
+                nvgpu_gv100_init_os_ops(l);
+                break;
         default:
                 break;
         }
diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c
new file mode 100644
index 00000000..13ce73e6
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "os_linux.h"
+
+#include "debug_clk_gp106.h"
+
+static struct nvgpu_os_linux_ops gp106_os_linux_ops = {
+        .clk = {
+                .init_debugfs = gp106_clk_init_debugfs,
+        },
+};
+
+void nvgpu_gp106_init_os_ops(struct nvgpu_os_linux *l)
+{
+        l->ops.clk = gp106_os_linux_ops.clk;
+}
diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h
new file mode 100644
index 00000000..7d423d5d
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/os_ops_gp106.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_OS_OPS_GP106_H
+#define __LINUX_OS_OPS_GP106_H
+
+void nvgpu_gp106_init_os_ops(struct nvgpu_os_linux *l);
+
+#endif
diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c
new file mode 100644
index 00000000..9236286b
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2018, NVIDIA Corporation.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "os_linux.h"
+
+#include "debug_clk_gp106.h"
+
+static struct nvgpu_os_linux_ops gv100_os_linux_ops = {
+        .clk = {
+                .init_debugfs = gp106_clk_init_debugfs,
+        },
+};
+
+void nvgpu_gv100_init_os_ops(struct nvgpu_os_linux *l)
+{
+        l->ops.clk = gv100_os_linux_ops.clk;
+}
diff --git a/drivers/gpu/nvgpu/os/linux/os_ops_gv100.h b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.h
new file mode 100644
index 00000000..43923b27
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/os_ops_gv100.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __LINUX_OS_OPS_GV100_H
+#define __LINUX_OS_OPS_GV100_H
+
+void nvgpu_gv100_init_os_ops(struct nvgpu_os_linux *l);
+
+#endif