gpu: nvgpu: rename ops.mm.get_physical_addr_bits

Rename get_physical_addr_bits and related functions to something that
more clearly conveys what they are doing. The basic idea of these
functions is to translate from a physical GPU address to a IOMMU GPU
address. To do that a particular bit (that varies from chip to chip)
is added to the physical address.

JIRA NVGPU-68

Change-Id: I536cc595c4397aad69a24f740bc74db03f52bc0a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1542966
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

12 files changed, 25 insertions, 25 deletions

diff --git a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c
index 8cf3011e..0be41a44 100644
--- a/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/linux/nvgpu_mem.c
@@ -268,7 +268,7 @@ u64 nvgpu_mem_get_addr_sgl(struct gk20a *g, struct scatterlist *sgl)
         if (sg_dma_address(sgl) == DMA_ERROR_CODE)
                 return 0;
 
-        return gk20a_mm_smmu_vaddr_translate(g, sg_dma_address(sgl));
+        return nvgpu_mem_iommu_translate(g, sg_dma_address(sgl));
 }
 
 /*
@@ -452,8 +452,8 @@ static u64 nvgpu_mem_linux_sgl_gpu_addr(struct gk20a *g, void *sgl,
         if (sg_dma_address((struct scatterlist *)sgl) == DMA_ERROR_CODE)
                 return 0;
 
-        return gk20a_mm_smmu_vaddr_translate(g,
-                        sg_dma_address((struct scatterlist *)sgl));
+        return nvgpu_mem_iommu_translate(g,
+                                sg_dma_address((struct scatterlist *)sgl));
 }
 
 static void nvgpu_mem_linux_sgl_free(struct gk20a *g, struct nvgpu_sgt *sgt)
diff --git a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
index 52d20883..faee482d 100644
--- a/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
+++ b/drivers/gpu/nvgpu/common/mm/nvgpu_mem.c
@@ -22,6 +22,7 @@
 
 #include <nvgpu/kmem.h>
 #include <nvgpu/nvgpu_mem.h>
+#include <nvgpu/dma.h>
 
 #include "gk20a/gk20a.h"
 
@@ -56,3 +57,14 @@ void nvgpu_sgt_free(struct nvgpu_sgt *sgt, struct gk20a *g)
         if (sgt && sgt->ops->sgt_free)
                 sgt->ops->sgt_free(g, sgt);
 }
+
+u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys)
+{
+        /* ensure it is not vidmem allocation */
+        WARN_ON(is_vidmem_page_alloc(phys));
+
+        if (nvgpu_iommuable(g) && g->ops.mm.get_iommu_bit)
+                return phys | 1ULL << g->ops.mm.get_iommu_bit(g);
+
+        return phys;
+}
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 8dabee63..db38fae4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -741,7 +741,7 @@ struct gpu_ops {
                                           struct nvgpu_mem *mem, int size);
                 u32 (*get_big_page_sizes)(void);
                 u32 (*get_default_big_page_size)(void);
-                u32 (*get_physical_addr_bits)(struct gk20a *g);
+                u32 (*get_iommu_bit)(struct gk20a *g);
                 int (*init_mm_setup_hw)(struct gk20a *g);
                 bool (*is_bar1_supported)(struct gk20a *g);
                 int (*init_bar2_vm)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 3d1f8d28..795f7bda 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -1271,17 +1271,6 @@ dma_addr_t gk20a_mm_gpuva_to_iova_base(struct vm_gk20a *vm, u64 gpu_vaddr)
         return addr;
 }
 
-u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, u64 iova)
-{
-        /* ensure it is not vidmem allocation */
-        WARN_ON(is_vidmem_page_alloc(iova));
-
-        if (nvgpu_iommuable(g) && g->ops.mm.get_physical_addr_bits)
-                return iova | 1ULL << g->ops.mm.get_physical_addr_bits(g);
-
-        return iova;
-}
-
 /* for gk20a the "video memory" apertures here are misnomers. */
 static inline u32 big_valid_pde0_bits(struct gk20a *g,
                                       struct nvgpu_gmmu_pd *pd, u64 addr)
@@ -2170,7 +2159,7 @@ int gk20a_mm_suspend(struct gk20a *g)
         return 0;
 }
 
-u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g)
+u32 gk20a_mm_get_iommu_bit(struct gk20a *g)
 {
         return 34;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
index 13a3dcd0..9f03a495 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.h
@@ -342,8 +342,6 @@ void gk20a_mm_dump_vm(struct vm_gk20a *vm,
 
 int gk20a_mm_suspend(struct gk20a *g);
 
-u64 gk20a_mm_smmu_vaddr_translate(struct gk20a *g, dma_addr_t iova);
-
 void gk20a_mm_ltc_isr(struct gk20a *g);
 
 bool gk20a_mm_mmu_debug_mode_enabled(struct gk20a *g);
@@ -420,7 +418,7 @@ void pde_range_from_vaddr_range(struct vm_gk20a *vm,
                                               u64 addr_lo, u64 addr_hi,
                                               u32 *pde_lo, u32 *pde_hi);
 int gk20a_mm_pde_coverage_bit_count(struct vm_gk20a *vm);
-u32 gk20a_mm_get_physical_addr_bits(struct gk20a *g);
+u32 gk20a_mm_get_iommu_bit(struct gk20a *g);
 
 const struct gk20a_mmu_level *gk20a_mm_get_mmu_levels(struct gk20a *g,
                                                       u32 big_page_size);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index ceef80bf..98c4ddfb 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -436,7 +436,7 @@ static const struct gpu_ops gm20b_ops = {
                 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
                 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
                 .gpu_phys_addr = gm20b_gpu_phys_addr,
-                .get_physical_addr_bits = gk20a_mm_get_physical_addr_bits,
+                .get_iommu_bit = gk20a_mm_get_iommu_bit,
                 .get_mmu_levels = gk20a_mm_get_mmu_levels,
                 .init_pdb = gk20a_mm_init_pdb,
                 .init_mm_setup_hw = gk20a_init_mm_setup_hw,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 90a513d6..89fe66c9 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -515,7 +515,6 @@ static const struct gpu_ops gp106_ops = {
                 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
                 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
                 .gpu_phys_addr = gm20b_gpu_phys_addr,
-                .get_physical_addr_bits = NULL,
                 .get_mmu_levels = gp10b_mm_get_mmu_levels,
                 .init_pdb = gp10b_mm_init_pdb,
                 .init_mm_setup_hw = gp10b_init_mm_setup_hw,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index e64bb9cc..0db6b3f7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -478,7 +478,7 @@ static const struct gpu_ops gp10b_ops = {
                 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
                 .get_default_big_page_size = gp10b_mm_get_default_big_page_size,
                 .gpu_phys_addr = gm20b_gpu_phys_addr,
-                .get_physical_addr_bits = gp10b_mm_get_physical_addr_bits,
+                .get_iommu_bit = gp10b_mm_get_iommu_bit,
                 .get_mmu_levels = gp10b_mm_get_mmu_levels,
                 .init_pdb = gp10b_mm_init_pdb,
                 .init_mm_setup_hw = gp10b_init_mm_setup_hw,
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
index 96da6cf5..06a9b929 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.c
@@ -41,7 +41,7 @@ u32 gp10b_mm_get_default_big_page_size(void)
         return SZ_64K;
 }
 
-u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g)
+u32 gp10b_mm_get_iommu_bit(struct gk20a *g)
 {
         return 36;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
index ab59069e..b6bcb04a 100644
--- a/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/mm_gp10b.h
@@ -29,7 +29,7 @@ struct nvgpu_mem;
 struct vm_gk20a;
 
 u32 gp10b_mm_get_default_big_page_size(void);
-u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g);
+u32 gp10b_mm_get_iommu_bit(struct gk20a *g);
 int gp10b_init_mm_setup_hw(struct gk20a *g);
 int gb10b_init_bar2_vm(struct gk20a *g);
 int gb10b_init_bar2_mm_hw_setup(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index b939cc33..c2f0e37b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -298,4 +298,6 @@ u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
 u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem,
                 u32 sysmem_mask, u32 vidmem_mask);
 
+u64 nvgpu_mem_iommu_translate(struct gk20a *g, u64 phys);
+
 #endif
diff --git a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
index 16bfb3a3..49517b9a 100644
--- a/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/mm_vgpu.c
@@ -379,7 +379,7 @@ void vgpu_init_mm_ops(struct gpu_ops *gops)
         gops->mm.l2_invalidate = vgpu_mm_l2_invalidate;
         gops->mm.l2_flush = vgpu_mm_l2_flush;
         gops->fb.tlb_invalidate = vgpu_mm_tlb_invalidate;
-        gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
+        gops->mm.get_iommu_bit = gk20a_mm_get_iommu_bit;
         gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
         gops->mm.init_mm_setup_hw = NULL;
 }