gpu: nvgpu: Move setting priv interrupt to priv_ring

Registers to set priv interrupts are in priv_ring, but the code was
in bus HAL. Move the code and related HALs to priv_ring instead.

JIRA NVGPU-588

Change-Id: I708d11f77405dbba86586a0d1da42f65bcc1de9d
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1730889
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

13 files changed, 31 insertions, 32 deletions

diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
index 46065579..62dd7450 100644
--- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
+++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.c
@@ -31,9 +31,6 @@
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_gr_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_timer_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
 
 void gk20a_bus_init_hw(struct gk20a *g)
 {
@@ -172,14 +169,3 @@ int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
 
         return 0;
 }
-
-void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g)
-{
-        /*
-         * Bug 1340570: increase the clock timeout to avoid potential
-         * operation failure at high gpcclk rate. Default values are 0x400.
-         */
-        nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
-        nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
-        nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
-}
diff --git a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h
index 8c07d1fe..1f81a4b0 100644
--- a/drivers/gpu/nvgpu/common/bus/bus_gk20a.h
+++ b/drivers/gpu/nvgpu/common/bus/bus_gk20a.h
@@ -32,6 +32,5 @@ void gk20a_bus_isr(struct gk20a *g);
 int gk20a_read_ptimer(struct gk20a *g, u64 *value);
 void gk20a_bus_init_hw(struct gk20a *g);
 int gk20a_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst);
-void gk20a_bus_set_ppriv_timeout_settings(struct gk20a *g);
 
 #endif /* GK20A_H */
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 77e6e759..2d304cff 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1128,7 +1128,6 @@ struct gpu_ops {
                         u32 source_id, u32 count,
                         struct nvgpu_cpu_time_correlation_sample *);
                 int (*bar1_bind)(struct gk20a *g, struct nvgpu_mem *bar1_inst);
-                void (*set_ppriv_timeout_settings)(struct gk20a *g);
         } bus;
 
         struct {
@@ -1179,6 +1178,7 @@ struct gpu_ops {
         struct {
                 void (*isr)(struct gk20a *g);
                 void (*decode_error_code)(struct gk20a *g, u32 error_code);
+                void (*set_ppriv_timeout_settings)(struct gk20a *g);
         } priv_ring;
         struct {
                 int (*check_priv_security)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 52346541..42e96715 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4502,8 +4502,8 @@ static int gk20a_init_gr_setup_hw(struct gk20a *g)
 
         gr_gk20a_zcull_init_hw(g, gr);
 
-        if (g->ops.bus.set_ppriv_timeout_settings)
-                g->ops.bus.set_ppriv_timeout_settings(g);
+        if (g->ops.priv_ring.set_ppriv_timeout_settings)
+                g->ops.priv_ring.set_ppriv_timeout_settings(g);
 
         /* enable fifo access */
         gk20a_writel(g, gr_gpfifo_ctl_r(),
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index dea42b55..adbaf94f 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -32,6 +32,7 @@
 #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
+#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
 
 void gk20a_enable_priv_ring(struct gk20a *g)
 {
@@ -103,3 +104,14 @@ void gk20a_priv_ring_isr(struct gk20a *g)
         if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v())
                 nvgpu_warn(g, "priv ringmaster intr ack too many retries");
 }
+
+void gk20a_priv_set_timeout_settings(struct gk20a *g)
+{
+        /*
+         * Bug 1340570: increase the clock timeout to avoid potential
+         * operation failure at high gpcclk rate. Default values are 0x400.
+         */
+        nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
+        nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
+        nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
+}
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
index ef564eeb..98040624 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
@@ -28,5 +28,6 @@ struct gpu_ops;
 
 void gk20a_priv_ring_isr(struct gk20a *g);
 void gk20a_enable_priv_ring(struct gk20a *g);
+void gk20a_priv_set_timeout_settings(struct gk20a *g);
 
 #endif /*__PRIV_RING_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index ccceab03..970d2d27 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -608,8 +608,6 @@ static const struct gpu_ops gm20b_ops = {
                 .read_ptimer = gk20a_read_ptimer,
                 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
                 .bar1_bind = gm20b_bus_bar1_bind,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -626,6 +624,8 @@ static const struct gpu_ops gm20b_ops = {
         },
         .priv_ring = {
                 .isr = gk20a_priv_ring_isr,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .fuse = {
                 .check_priv_security = gm20b_fuse_check_priv_security,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 7cfe4d76..6749dba7 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -726,8 +726,7 @@ static const struct gpu_ops gp106_ops = {
                 .read_ptimer = gk20a_read_ptimer,
                 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
                 .bar1_bind = gk20a_bus_bar1_bind,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
+
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -760,6 +759,8 @@ static const struct gpu_ops gp106_ops = {
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
                 .decode_error_code = gp10b_priv_ring_decode_error_code,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .fuse = {
                 .check_priv_security = gp106_fuse_check_priv_security,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 2d6479fc..47986f1b 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -656,8 +656,6 @@ static const struct gpu_ops gp10b_ops = {
                 .read_ptimer = gk20a_read_ptimer,
                 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
                 .bar1_bind = gk20a_bus_bar1_bind,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -675,6 +673,8 @@ static const struct gpu_ops gp10b_ops = {
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
                 .decode_error_code = gp10b_priv_ring_decode_error_code,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .fuse = {
                 .check_priv_security = gp10b_fuse_check_priv_security,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 961129c6..00c992bc 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -796,8 +796,6 @@ static const struct gpu_ops gv100_ops = {
                 .read_ptimer = gk20a_read_ptimer,
                 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
                 .bar1_bind = NULL,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -827,6 +825,8 @@ static const struct gpu_ops gv100_ops = {
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
                 .decode_error_code = gp10b_priv_ring_decode_error_code,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
 #if defined(CONFIG_TEGRA_NVLINK)
         .nvlink = {
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 2379c17b..a191c3fc 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -725,8 +725,6 @@ static const struct gpu_ops gv11b_ops = {
                 .read_ptimer = gk20a_read_ptimer,
                 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
                 .bar1_bind = NULL,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -744,6 +742,8 @@ static const struct gpu_ops gv11b_ops = {
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
                 .decode_error_code = gp10b_priv_ring_decode_error_code,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .fuse = {
                 .check_priv_security = gp10b_fuse_check_priv_security,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 3f6d4e0f..f4a87a74 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -529,8 +529,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .read_ptimer = vgpu_read_ptimer,
                 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
                 .bar1_bind = gk20a_bus_bar1_bind,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -548,6 +546,8 @@ static const struct gpu_ops vgpu_gp10b_ops = {
         },
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .fuse = {
                 .check_priv_security = vgpu_gp10b_fuse_check_priv_security,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 0a48e1ae..deecc0d8 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -577,8 +577,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .read_ptimer = vgpu_read_ptimer,
                 .get_timestamps_zipper = vgpu_get_timestamps_zipper,
                 .bar1_bind = NULL,
-                .set_ppriv_timeout_settings =
-                        gk20a_bus_set_ppriv_timeout_settings,
         },
 #if defined(CONFIG_GK20A_CYCLE_STATS)
         .css = {
@@ -596,6 +594,8 @@ static const struct gpu_ops vgpu_gv11b_ops = {
         },
         .priv_ring = {
                 .isr = gp10b_priv_ring_isr,
+                .set_ppriv_timeout_settings =
+                        gk20a_priv_set_timeout_settings,
         },
         .chip_init_gpu_characteristics = vgpu_gv11b_init_gpu_characteristics,
         .get_litter_value = gv11b_get_litter_value,