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authorSunny He <suhe@nvidia.com>2017-06-28 20:56:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-13 03:09:07 -0400
commitecf67ebbf69a9ab6481b1517b8920f7ac5828bb5 (patch)
tree87f9577885854817d46b0e7103933012040eb359
parent90d388ebf8d2f9f9d08f6a5c0f638aa8339c1f24 (diff)
gpu: nvgpu: Reorg falcon HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the falcon sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ib1aaaa248b079bb591ccfada3382b689452de0e9 Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1514012 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gk20a/flcn_gk20a.c7
-rw-r--r--drivers/gpu/nvgpu/gk20a/flcn_gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c7
-rw-r--r--drivers/gpu/nvgpu/gp106/flcn_gp106.c7
-rw-r--r--drivers/gpu/nvgpu/gp106/flcn_gp106.h8
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c5
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c5
7 files changed, 20 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
index 0ef10a56..a21342c5 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.c
@@ -382,7 +382,7 @@ void gk20a_falcon_ops(struct nvgpu_falcon *flcn)
382 gk20a_falcon_engine_dependency_ops(flcn); 382 gk20a_falcon_engine_dependency_ops(flcn);
383} 383}
384 384
385static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn) 385void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
386{ 386{
387 struct gk20a *g = flcn->g; 387 struct gk20a *g = flcn->g;
388 388
@@ -420,8 +420,3 @@ static void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
420 nvgpu_log_info(g, "falcon 0x%x not supported on %s", 420 nvgpu_log_info(g, "falcon 0x%x not supported on %s",
421 flcn->flcn_id, g->name); 421 flcn->flcn_id, g->name);
422} 422}
423
424void gk20a_falcon_init_hal(struct gpu_ops *gops)
425{
426 gops->falcon.falcon_hal_sw_init = gk20a_falcon_hal_sw_init;
427}
diff --git a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
index 049da562..7b342fdd 100644
--- a/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/flcn_gk20a.h
@@ -14,6 +14,6 @@
14#define __FLCN_GK20A_H__ 14#define __FLCN_GK20A_H__
15 15
16void gk20a_falcon_ops(struct nvgpu_falcon *flcn); 16void gk20a_falcon_ops(struct nvgpu_falcon *flcn);
17void gk20a_falcon_init_hal(struct gpu_ops *gops); 17void gk20a_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
18 18
19#endif /* __FLCN_GK20A_H__ */ 19#endif /* __FLCN_GK20A_H__ */
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index b16289f9..c6c7b590 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -200,7 +200,10 @@ static const struct gpu_ops gm20b_ops = {
200 gr_gm20b_pg_gr_load_gating_prod, 200 gr_gm20b_pg_gr_load_gating_prod,
201 }, 201 },
202 .cde = { 202 .cde = {
203 .get_program_numbers = gm20b_cde_get_program_numbers 203 .get_program_numbers = gm20b_cde_get_program_numbers,
204 },
205 .falcon = {
206 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
204 }, 207 },
205 .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, 208 .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
206 .get_litter_value = gm20b_get_litter_value, 209 .get_litter_value = gm20b_get_litter_value,
@@ -215,6 +218,7 @@ int gm20b_init_hal(struct gk20a *g)
215 gops->ltc = gm20b_ops.ltc; 218 gops->ltc = gm20b_ops.ltc;
216 gops->clock_gating = gm20b_ops.clock_gating; 219 gops->clock_gating = gm20b_ops.clock_gating;
217 gops->cde = gm20b_ops.cde; 220 gops->cde = gm20b_ops.cde;
221 gops->falcon = gm20b_ops.falcon;
218 222
219 /* Lone functions */ 223 /* Lone functions */
220 gops->chip_init_gpu_characteristics = 224 gops->chip_init_gpu_characteristics =
@@ -259,7 +263,6 @@ int gm20b_init_hal(struct gk20a *g)
259 gm20b_init_ce2(gops); 263 gm20b_init_ce2(gops);
260 gm20b_init_gr_ctx(gops); 264 gm20b_init_gr_ctx(gops);
261 gm20b_init_mm(gops); 265 gm20b_init_mm(gops);
262 gk20a_falcon_init_hal(gops);
263 gm20b_init_pmu_ops(gops); 266 gm20b_init_pmu_ops(gops);
264 gm20b_init_clk_ops(gops); 267 gm20b_init_clk_ops(gops);
265 gm20b_init_regops(gops); 268 gm20b_init_regops(gops);
diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.c b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
index 6ae0b7af..3cb51dcc 100644
--- a/drivers/gpu/nvgpu/gp106/flcn_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.c
@@ -40,7 +40,7 @@ static void gp106_falcon_ops(struct nvgpu_falcon *flcn)
40 gp106_falcon_engine_dependency_ops(flcn); 40 gp106_falcon_engine_dependency_ops(flcn);
41} 41}
42 42
43static void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn) 43void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
44{ 44{
45 struct gk20a *g = flcn->g; 45 struct gk20a *g = flcn->g;
46 46
@@ -78,8 +78,3 @@ static void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn)
78 nvgpu_info(g, "falcon 0x%x not supported on %s", 78 nvgpu_info(g, "falcon 0x%x not supported on %s",
79 flcn->flcn_id, g->name); 79 flcn->flcn_id, g->name);
80} 80}
81
82void gp106_falcon_init_hal(struct gpu_ops *gops)
83{
84 gops->falcon.falcon_hal_sw_init = gp106_falcon_hal_sw_init;
85}
diff --git a/drivers/gpu/nvgpu/gp106/flcn_gp106.h b/drivers/gpu/nvgpu/gp106/flcn_gp106.h
index d5ea14ae..e57100d5 100644
--- a/drivers/gpu/nvgpu/gp106/flcn_gp106.h
+++ b/drivers/gpu/nvgpu/gp106/flcn_gp106.h
@@ -10,9 +10,9 @@
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details. 11 * more details.
12 */ 12 */
13#ifndef __FLCN_GK20A_H__ 13#ifndef __FLCN_GP106_H__
14#define __FLCN_GK20A_H__ 14#define __FLCN_GP106_H__
15 15
16void gp106_falcon_init_hal(struct gpu_ops *gops); 16void gp106_falcon_hal_sw_init(struct nvgpu_falcon *flcn);
17 17
18#endif /* __FLCN_GK20A_H__ */ 18#endif /* __FLCN_GP106_H__ */
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 555a2192..29b52e44 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -259,6 +259,9 @@ static const struct gpu_ops gp106_ops = {
259 .enable_shadow_rom = xve_enable_shadow_rom_gp106, 259 .enable_shadow_rom = xve_enable_shadow_rom_gp106,
260 .disable_shadow_rom = xve_disable_shadow_rom_gp106, 260 .disable_shadow_rom = xve_disable_shadow_rom_gp106,
261 }, 261 },
262 .falcon = {
263 .falcon_hal_sw_init = gp106_falcon_hal_sw_init,
264 },
262 .get_litter_value = gp106_get_litter_value, 265 .get_litter_value = gp106_get_litter_value,
263 .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, 266 .chip_init_gpu_characteristics = gp106_init_gpu_characteristics,
264 .bios_init = gm206_bios_init, 267 .bios_init = gm206_bios_init,
@@ -275,6 +278,7 @@ int gp106_init_hal(struct gk20a *g)
275 gops->clock_gating = gp106_ops.clock_gating; 278 gops->clock_gating = gp106_ops.clock_gating;
276 gops->cde = gp106_ops.cde; 279 gops->cde = gp106_ops.cde;
277 gops->xve = gp106_ops.xve; 280 gops->xve = gp106_ops.xve;
281 gops->falcon = gp106_ops.falcon;
278 282
279 /* Lone functions */ 283 /* Lone functions */
280 gops->get_litter_value = gp106_ops.get_litter_value; 284 gops->get_litter_value = gp106_ops.get_litter_value;
@@ -295,7 +299,6 @@ int gp106_init_hal(struct gk20a *g)
295 gp10b_init_ce(gops); 299 gp10b_init_ce(gops);
296 gp106_init_gr_ctx(gops); 300 gp106_init_gr_ctx(gops);
297 gp106_init_mm(gops); 301 gp106_init_mm(gops);
298 gp106_falcon_init_hal(gops);
299 gp106_init_pmu_ops(gops); 302 gp106_init_pmu_ops(gops);
300 gk20a_init_debug_ops(gops); 303 gk20a_init_debug_ops(gops);
301 gk20a_init_dbg_session_ops(gops); 304 gk20a_init_dbg_session_ops(gops);
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 8609605b..d004cf3d 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -212,6 +212,9 @@ static const struct gpu_ops gp10b_ops = {
212 .need_scatter_buffer = gp10b_need_scatter_buffer, 212 .need_scatter_buffer = gp10b_need_scatter_buffer,
213 .populate_scatter_buffer = gp10b_populate_scatter_buffer, 213 .populate_scatter_buffer = gp10b_populate_scatter_buffer,
214 }, 214 },
215 .falcon = {
216 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
217 },
215 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, 218 .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics,
216 .get_litter_value = gp10b_get_litter_value, 219 .get_litter_value = gp10b_get_litter_value,
217}; 220};
@@ -225,6 +228,7 @@ int gp10b_init_hal(struct gk20a *g)
225 gops->ltc = gp10b_ops.ltc; 228 gops->ltc = gp10b_ops.ltc;
226 gops->clock_gating = gp10b_ops.clock_gating; 229 gops->clock_gating = gp10b_ops.clock_gating;
227 gops->cde = gp10b_ops.cde; 230 gops->cde = gp10b_ops.cde;
231 gops->falcon = gp10b_ops.falcon;
228 232
229 /* Lone Functions */ 233 /* Lone Functions */
230 gops->chip_init_gpu_characteristics = 234 gops->chip_init_gpu_characteristics =
@@ -279,7 +283,6 @@ int gp10b_init_hal(struct gk20a *g)
279 gp10b_init_ce(gops); 283 gp10b_init_ce(gops);
280 gp10b_init_gr_ctx(gops); 284 gp10b_init_gr_ctx(gops);
281 gp10b_init_mm(gops); 285 gp10b_init_mm(gops);
282 gk20a_falcon_init_hal(gops);
283 gp10b_init_pmu_ops(gops); 286 gp10b_init_pmu_ops(gops);
284 gk20a_init_debug_ops(gops); 287 gk20a_init_debug_ops(gops);
285 gk20a_init_dbg_session_ops(gops); 288 gk20a_init_dbg_session_ops(gops);