diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-06-07 05:23:58 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-15 08:43:48 -0400 |
commit | eb8db3e4df159210ca9c7f834dbbc939a5c67a96 (patch) | |
tree | f11713d5af4ec8b58929505e5414c52b9482ca0a | |
parent | f6c921ec97323c1eab7d3b8a0cda73abf041a00f (diff) |
gpu: nvgpu: add APIs to export fuse offsets
Add below new APIs in common/linux/fuse.c and export them from
include/nvgpu/fuse.h to read/write specific tegra fuse offsets
void nvgpu_tegra_fuse_write_bypass(u32 val);
void nvgpu_tegra_fuse_write_access_sw(u32 val);
void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val);
void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val);
int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val);
int nvgpu_tegra_fuse_read_reserved_calib(u32 *val);
These APIs are needed to remove nvgpu's direct
dependency on platform specific <soc/tegra/fuse.h> header
Remove below generic APIs since they are no longer needed :
nvgpu_tegra_fuse_read()
nvgpu_tegra_fuse_write()
Jira NVGPU-75
Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1497517
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/fuse.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/fuse.h | 10 |
2 files changed, 37 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/fuse.c b/drivers/gpu/nvgpu/common/linux/fuse.c index 5c832a2a..993cbc5a 100644 --- a/drivers/gpu/nvgpu/common/linux/fuse.c +++ b/drivers/gpu/nvgpu/common/linux/fuse.c | |||
@@ -15,17 +15,41 @@ | |||
15 | 15 | ||
16 | #include <nvgpu/fuse.h> | 16 | #include <nvgpu/fuse.h> |
17 | 17 | ||
18 | int nvgpu_tegra_fuse_read(unsigned long offset, u32 *value) | 18 | int nvgpu_tegra_get_gpu_speedo_id(void) |
19 | { | 19 | { |
20 | return tegra_fuse_readl(offset, value); | 20 | return tegra_sku_info.gpu_speedo_id; |
21 | } | 21 | } |
22 | 22 | ||
23 | void nvgpu_tegra_fuse_write(u32 value, unsigned long offset) | 23 | /* |
24 | * Use tegra_fuse_control_read/write() APIs for fuse offsets upto 0x100 | ||
25 | * Use tegra_fuse_readl/writel() APIs for fuse offsets above 0x100 | ||
26 | */ | ||
27 | void nvgpu_tegra_fuse_write_bypass(u32 val) | ||
24 | { | 28 | { |
25 | tegra_fuse_control_write(value, offset); | 29 | tegra_fuse_control_write(val, FUSE_FUSEBYPASS_0); |
26 | } | 30 | } |
27 | 31 | ||
28 | int nvgpu_tegra_get_gpu_speedo_id(void) | 32 | void nvgpu_tegra_fuse_write_access_sw(u32 val) |
29 | { | 33 | { |
30 | return tegra_sku_info.gpu_speedo_id; | 34 | tegra_fuse_control_write(val, FUSE_WRITE_ACCESS_SW_0); |
35 | } | ||
36 | |||
37 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val) | ||
38 | { | ||
39 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC0_DISABLE_0); | ||
40 | } | ||
41 | |||
42 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val) | ||
43 | { | ||
44 | tegra_fuse_writel(val, FUSE_OPT_GPU_TPC1_DISABLE_0); | ||
45 | } | ||
46 | |||
47 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val) | ||
48 | { | ||
49 | return tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, val); | ||
50 | } | ||
51 | |||
52 | int nvgpu_tegra_fuse_read_reserved_calib(u32 *val) | ||
53 | { | ||
54 | return tegra_fuse_readl(FUSE_RESERVED_CALIB0_0, val); | ||
31 | } | 55 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h index 1e306b2d..3650fd58 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h +++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h | |||
@@ -13,9 +13,13 @@ | |||
13 | #ifndef __NVGPU_FUSE_H__ | 13 | #ifndef __NVGPU_FUSE_H__ |
14 | #define __NVGPU_FUSE_H__ | 14 | #define __NVGPU_FUSE_H__ |
15 | 15 | ||
16 | int nvgpu_tegra_fuse_read(unsigned long offset, u32 *value); | ||
17 | void nvgpu_tegra_fuse_write(u32 value, unsigned long offset); | ||
18 | |||
19 | int nvgpu_tegra_get_gpu_speedo_id(void); | 16 | int nvgpu_tegra_get_gpu_speedo_id(void); |
20 | 17 | ||
18 | void nvgpu_tegra_fuse_write_bypass(u32 val); | ||
19 | void nvgpu_tegra_fuse_write_access_sw(u32 val); | ||
20 | void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); | ||
21 | void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); | ||
22 | int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); | ||
23 | int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); | ||
24 | |||
21 | #endif | 25 | #endif |