diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-10-11 17:58:57 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-26 17:35:38 -0400 |
commit | e49d93a960f8995affeb4541941eb7f16d04eafd (patch) | |
tree | 7b5eb1365bfee8a237ddf7d8e0b02959e50f5704 | |
parent | 9eebb7831facaa16b2975f50a716d2986c67b699 (diff) |
gpu: nvgpu: Linux specific GPU characteristics flags
Make GPU characteristics flags specific to Linux code only. The
rest of driver is moved to using nvgpu_is_enabled() API.
JIRA NVGPU-259
Change-Id: I2faf46ef64c964361c267887b28c9d19806d6d51
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1583876
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_channel.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | 87 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/mm/vm.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 20 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gp10b.c | 54 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/enabled.h | 64 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/vgpu.c | 6 |
12 files changed, 209 insertions, 72 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c index ed00ad31..ee4755c8 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_channel.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <nvgpu/log.h> | 28 | #include <nvgpu/log.h> |
29 | #include <nvgpu/list.h> | 29 | #include <nvgpu/list.h> |
30 | #include <nvgpu/debug.h> | 30 | #include <nvgpu/debug.h> |
31 | #include <nvgpu/enabled.h> | ||
31 | 32 | ||
32 | #include "gk20a/gk20a.h" | 33 | #include "gk20a/gk20a.h" |
33 | #include "gk20a/ctxsw_trace_gk20a.h" | 34 | #include "gk20a/ctxsw_trace_gk20a.h" |
@@ -99,8 +100,7 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch, | |||
99 | void *virtual_address; | 100 | void *virtual_address; |
100 | 101 | ||
101 | /* is it allowed to handle calls for current GPU? */ | 102 | /* is it allowed to handle calls for current GPU? */ |
102 | if (0 == (ch->g->gpu_characteristics.flags & | 103 | if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS)) |
103 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS)) | ||
104 | return -ENOSYS; | 104 | return -ENOSYS; |
105 | 105 | ||
106 | if (args->dmabuf_fd && !ch->cyclestate.cyclestate_buffer_handler) { | 106 | if (args->dmabuf_fd && !ch->cyclestate.cyclestate_buffer_handler) { |
@@ -176,8 +176,7 @@ static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch, | |||
176 | int ret; | 176 | int ret; |
177 | 177 | ||
178 | /* is it allowed to handle calls for current GPU? */ | 178 | /* is it allowed to handle calls for current GPU? */ |
179 | if (0 == (ch->g->gpu_characteristics.flags & | 179 | if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT)) |
180 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT)) | ||
181 | return -ENOSYS; | 180 | return -ENOSYS; |
182 | 181 | ||
183 | if (!args->dmabuf_fd) | 182 | if (!args->dmabuf_fd) |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index 4bb79375..6c9fc26f 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -20,6 +20,7 @@ | |||
20 | #include <linux/anon_inodes.h> | 20 | #include <linux/anon_inodes.h> |
21 | #include <linux/fs.h> | 21 | #include <linux/fs.h> |
22 | #include <uapi/linux/nvgpu.h> | 22 | #include <uapi/linux/nvgpu.h> |
23 | #include <uapi/linux/nvgpu-t18x.h> | ||
23 | 24 | ||
24 | #include <nvgpu/bitops.h> | 25 | #include <nvgpu/bitops.h> |
25 | #include <nvgpu/kmem.h> | 26 | #include <nvgpu/kmem.h> |
@@ -27,10 +28,14 @@ | |||
27 | #include <nvgpu/bus.h> | 28 | #include <nvgpu/bus.h> |
28 | #include <nvgpu/vidmem.h> | 29 | #include <nvgpu/vidmem.h> |
29 | #include <nvgpu/log.h> | 30 | #include <nvgpu/log.h> |
31 | #include <nvgpu/enabled.h> | ||
30 | 32 | ||
31 | #include <nvgpu/linux/vidmem.h> | 33 | #include <nvgpu/linux/vidmem.h> |
32 | 34 | ||
33 | #include "ioctl_ctrl.h" | 35 | #include "ioctl_ctrl.h" |
36 | #ifdef CONFIG_TEGRA_19x_GPU | ||
37 | #include "common/linux/ioctl_ctrl_t19x.h" | ||
38 | #endif | ||
34 | #include "ioctl_tsg.h" | 39 | #include "ioctl_tsg.h" |
35 | #include "ioctl_channel.h" | 40 | #include "ioctl_channel.h" |
36 | #include "gk20a/gk20a.h" | 41 | #include "gk20a/gk20a.h" |
@@ -113,6 +118,77 @@ int gk20a_ctrl_dev_release(struct inode *inode, struct file *filp) | |||
113 | return 0; | 118 | return 0; |
114 | } | 119 | } |
115 | 120 | ||
121 | struct nvgpu_flags_mapping { | ||
122 | u64 ioctl_flag; | ||
123 | int enabled_flag; | ||
124 | }; | ||
125 | |||
126 | static struct nvgpu_flags_mapping flags_mapping[] = { | ||
127 | {NVGPU_GPU_FLAGS_HAS_SYNCPOINTS, | ||
128 | NVGPU_HAS_SYNCPOINTS}, | ||
129 | {NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS, | ||
130 | NVGPU_SUPPORT_PARTIAL_MAPPINGS}, | ||
131 | {NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS, | ||
132 | NVGPU_SUPPORT_SPARSE_ALLOCS}, | ||
133 | {NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS, | ||
134 | NVGPU_SUPPORT_SYNC_FENCE_FDS}, | ||
135 | {NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS, | ||
136 | NVGPU_SUPPORT_CYCLE_STATS}, | ||
137 | {NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT, | ||
138 | NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT}, | ||
139 | {NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS, | ||
140 | NVGPU_SUPPORT_USERSPACE_MANAGED_AS}, | ||
141 | {NVGPU_GPU_FLAGS_SUPPORT_TSG, | ||
142 | NVGPU_SUPPORT_TSG}, | ||
143 | {NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS, | ||
144 | NVGPU_SUPPORT_CLOCK_CONTROLS}, | ||
145 | {NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE, | ||
146 | NVGPU_SUPPORT_GET_VOLTAGE}, | ||
147 | {NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT, | ||
148 | NVGPU_SUPPORT_GET_CURRENT}, | ||
149 | {NVGPU_GPU_FLAGS_SUPPORT_GET_POWER, | ||
150 | NVGPU_SUPPORT_GET_POWER}, | ||
151 | {NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE, | ||
152 | NVGPU_SUPPORT_GET_TEMPERATURE}, | ||
153 | {NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT, | ||
154 | NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT}, | ||
155 | {NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS, | ||
156 | NVGPU_SUPPORT_DEVICE_EVENTS}, | ||
157 | {NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE, | ||
158 | NVGPU_SUPPORT_FECS_CTXSW_TRACE}, | ||
159 | {NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING, | ||
160 | NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING}, | ||
161 | {NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL, | ||
162 | NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL}, | ||
163 | {NVGPU_GPU_FLAGS_SUPPORT_IO_COHERENCE, | ||
164 | NVGPU_SUPPORT_IO_COHERENCE}, | ||
165 | {NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST, | ||
166 | NVGPU_SUPPORT_RESCHEDULE_RUNLIST}, | ||
167 | {NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL, | ||
168 | NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL}, | ||
169 | {NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF, | ||
170 | NVGPU_ECC_ENABLED_SM_LRF}, | ||
171 | {NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM, | ||
172 | NVGPU_ECC_ENABLED_SM_SHM}, | ||
173 | {NVGPU_GPU_FLAGS_ECC_ENABLED_TEX, | ||
174 | NVGPU_ECC_ENABLED_TEX}, | ||
175 | {NVGPU_GPU_FLAGS_ECC_ENABLED_LTC, | ||
176 | NVGPU_ECC_ENABLED_LTC}, | ||
177 | }; | ||
178 | |||
179 | static u64 nvgpu_ctrl_ioctl_gpu_characteristics_flags(struct gk20a *g) | ||
180 | { | ||
181 | unsigned int i; | ||
182 | u64 ioctl_flags = 0; | ||
183 | |||
184 | for (i = 0; i < sizeof(flags_mapping)/sizeof(*flags_mapping); i++) { | ||
185 | if (nvgpu_is_enabled(g, flags_mapping[i].enabled_flag)) | ||
186 | ioctl_flags |= flags_mapping[i].ioctl_flag; | ||
187 | } | ||
188 | |||
189 | return ioctl_flags; | ||
190 | } | ||
191 | |||
116 | static long | 192 | static long |
117 | gk20a_ctrl_ioctl_gpu_characteristics( | 193 | gk20a_ctrl_ioctl_gpu_characteristics( |
118 | struct gk20a *g, | 194 | struct gk20a *g, |
@@ -121,6 +197,11 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
121 | struct nvgpu_gpu_characteristics *pgpu = &g->gpu_characteristics; | 197 | struct nvgpu_gpu_characteristics *pgpu = &g->gpu_characteristics; |
122 | long err = 0; | 198 | long err = 0; |
123 | 199 | ||
200 | pgpu->flags = nvgpu_ctrl_ioctl_gpu_characteristics_flags(g); | ||
201 | #ifdef CONFIG_TEGRA_19x_GPU | ||
202 | pgpu->flags |= nvgpu_ctrl_ioctl_gpu_characteristics_flags_t19x(g); | ||
203 | #endif | ||
204 | |||
124 | if (request->gpu_characteristics_buf_size > 0) { | 205 | if (request->gpu_characteristics_buf_size > 0) { |
125 | size_t write_size = sizeof(*pgpu); | 206 | size_t write_size = sizeof(*pgpu); |
126 | 207 | ||
@@ -1108,7 +1189,7 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g, | |||
1108 | if (args->reserved) | 1189 | if (args->reserved) |
1109 | return -EINVAL; | 1190 | return -EINVAL; |
1110 | 1191 | ||
1111 | if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE)) | 1192 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE)) |
1112 | return -EINVAL; | 1193 | return -EINVAL; |
1113 | 1194 | ||
1114 | err = gk20a_busy(g); | 1195 | err = gk20a_busy(g); |
@@ -1144,7 +1225,7 @@ static int nvgpu_gpu_get_current(struct gk20a *g, | |||
1144 | if (args->reserved[0] || args->reserved[1] || args->reserved[2]) | 1225 | if (args->reserved[0] || args->reserved[1] || args->reserved[2]) |
1145 | return -EINVAL; | 1226 | return -EINVAL; |
1146 | 1227 | ||
1147 | if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT)) | 1228 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_CURRENT)) |
1148 | return -EINVAL; | 1229 | return -EINVAL; |
1149 | 1230 | ||
1150 | err = gk20a_busy(g); | 1231 | err = gk20a_busy(g); |
@@ -1168,7 +1249,7 @@ static int nvgpu_gpu_get_power(struct gk20a *g, | |||
1168 | if (args->reserved[0] || args->reserved[1] || args->reserved[2]) | 1249 | if (args->reserved[0] || args->reserved[1] || args->reserved[2]) |
1169 | return -EINVAL; | 1250 | return -EINVAL; |
1170 | 1251 | ||
1171 | if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_SUPPORT_GET_POWER)) | 1252 | if (!nvgpu_is_enabled(g, NVGPU_SUPPORT_GET_POWER)) |
1172 | return -EINVAL; | 1253 | return -EINVAL; |
1173 | 1254 | ||
1174 | err = gk20a_busy(g); | 1255 | err = gk20a_busy(g); |
diff --git a/drivers/gpu/nvgpu/common/mm/vm.c b/drivers/gpu/nvgpu/common/mm/vm.c index c6c99b31..88af6456 100644 --- a/drivers/gpu/nvgpu/common/mm/vm.c +++ b/drivers/gpu/nvgpu/common/mm/vm.c | |||
@@ -175,7 +175,7 @@ static int nvgpu_init_sema_pool(struct vm_gk20a *vm) | |||
175 | /* | 175 | /* |
176 | * Don't waste the memory on semaphores if we don't need them. | 176 | * Don't waste the memory on semaphores if we don't need them. |
177 | */ | 177 | */ |
178 | if (g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_HAS_SYNCPOINTS) | 178 | if (nvgpu_is_enabled(g, NVGPU_HAS_SYNCPOINTS)) |
179 | return 0; | 179 | return 0; |
180 | 180 | ||
181 | if (vm->sema_pool) | 181 | if (vm->sema_pool) |
@@ -520,7 +520,7 @@ static void __nvgpu_vm_remove(struct vm_gk20a *vm) | |||
520 | * pool involves unmapping a GMMU mapping which means aquiring the | 520 | * pool involves unmapping a GMMU mapping which means aquiring the |
521 | * update_gmmu_lock. | 521 | * update_gmmu_lock. |
522 | */ | 522 | */ |
523 | if (!(g->gpu_characteristics.flags & NVGPU_GPU_FLAGS_HAS_SYNCPOINTS)) { | 523 | if (!nvgpu_is_enabled(g, NVGPU_HAS_SYNCPOINTS)) { |
524 | if (vm->sema_pool) { | 524 | if (vm->sema_pool) { |
525 | nvgpu_semaphore_pool_unmap(vm->sema_pool, vm); | 525 | nvgpu_semaphore_pool_unmap(vm->sema_pool, vm); |
526 | nvgpu_semaphore_pool_put(vm->sema_pool); | 526 | nvgpu_semaphore_pool_put(vm->sema_pool); |
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index 12d7dcb9..1517d25a 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include <nvgpu/thread.h> | 33 | #include <nvgpu/thread.h> |
34 | #include <nvgpu/barrier.h> | 34 | #include <nvgpu/barrier.h> |
35 | #include <nvgpu/mm.h> | 35 | #include <nvgpu/mm.h> |
36 | #include <nvgpu/enabled.h> | ||
36 | 37 | ||
37 | #include "ctxsw_trace_gk20a.h" | 38 | #include "ctxsw_trace_gk20a.h" |
38 | #include "fecs_trace_gk20a.h" | 39 | #include "fecs_trace_gk20a.h" |
@@ -594,8 +595,7 @@ int gk20a_fecs_trace_init(struct gk20a *g) | |||
594 | 595 | ||
595 | hash_init(trace->pid_hash_table); | 596 | hash_init(trace->pid_hash_table); |
596 | 597 | ||
597 | g->gpu_characteristics.flags |= | 598 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); |
598 | NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE; | ||
599 | 599 | ||
600 | gk20a_fecs_trace_debugfs_init(g); | 600 | gk20a_fecs_trace_debugfs_init(g); |
601 | 601 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index e3c2397c..2b99b52c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -417,24 +417,26 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) | |||
417 | gpu->available_big_page_sizes |= g->ops.mm.get_big_page_sizes(); | 417 | gpu->available_big_page_sizes |= g->ops.mm.get_big_page_sizes(); |
418 | } | 418 | } |
419 | 419 | ||
420 | gpu->flags = NVGPU_GPU_FLAGS_SUPPORT_PARTIAL_MAPPINGS | | 420 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_PARTIAL_MAPPINGS, true); |
421 | NVGPU_GPU_FLAGS_SUPPORT_MAP_DIRECT_KIND_CTRL; | 421 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL, true); |
422 | 422 | ||
423 | if (IS_ENABLED(CONFIG_SYNC)) | 423 | if (IS_ENABLED(CONFIG_SYNC)) |
424 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_SYNC_FENCE_FDS; | 424 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SYNC_FENCE_FDS, true); |
425 | 425 | ||
426 | if (g->ops.mm.support_sparse && g->ops.mm.support_sparse(g)) | 426 | if (g->ops.mm.support_sparse && g->ops.mm.support_sparse(g)) |
427 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_SPARSE_ALLOCS; | 427 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SPARSE_ALLOCS, true); |
428 | 428 | ||
429 | if (gk20a_platform_has_syncpoints(g)) | 429 | if (gk20a_platform_has_syncpoints(g)) |
430 | gpu->flags |= NVGPU_GPU_FLAGS_HAS_SYNCPOINTS; | 430 | __nvgpu_set_enabled(g, NVGPU_HAS_SYNCPOINTS, true); |
431 | 431 | ||
432 | /* | 432 | /* |
433 | * Fast submits are supported as long as the user doesn't request | 433 | * Fast submits are supported as long as the user doesn't request |
434 | * anything that depends on job tracking. (Here, fast means strictly no | 434 | * anything that depends on job tracking. (Here, fast means strictly no |
435 | * metadata, just the gpfifo contents are copied and gp_put updated). | 435 | * metadata, just the gpfifo contents are copied and gp_put updated). |
436 | */ | 436 | */ |
437 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING; | 437 | __nvgpu_set_enabled(g, |
438 | NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING, | ||
439 | true); | ||
438 | 440 | ||
439 | /* | 441 | /* |
440 | * Sync framework requires deferred job cleanup, wrapping syncs in FDs, | 442 | * Sync framework requires deferred job cleanup, wrapping syncs in FDs, |
@@ -443,13 +445,15 @@ int gk20a_init_gpu_characteristics(struct gk20a *g) | |||
443 | * that depends on deferred cleanup. | 445 | * that depends on deferred cleanup. |
444 | */ | 446 | */ |
445 | if (!gk20a_channel_sync_needs_sync_framework(g)) | 447 | if (!gk20a_channel_sync_needs_sync_framework(g)) |
446 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_DETERMINISTIC_SUBMIT_FULL; | 448 | __nvgpu_set_enabled(g, |
449 | NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL, | ||
450 | true); | ||
447 | 451 | ||
448 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_USERSPACE_MANAGED_AS; | 452 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_USERSPACE_MANAGED_AS, true); |
449 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_TSG; | 453 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_TSG, true); |
450 | 454 | ||
451 | if (g->ops.clk_arb.get_arbiter_clk_domains) | 455 | if (g->ops.clk_arb.get_arbiter_clk_domains) |
452 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_CLOCK_CONTROLS; | 456 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CLOCK_CONTROLS, true); |
453 | 457 | ||
454 | gpu->gpc_mask = (1 << g->gr.gpc_count)-1; | 458 | gpu->gpc_mask = (1 << g->gr.gpc_count)-1; |
455 | 459 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c10517b7..7ec8e2cb 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1126,10 +1126,8 @@ u32 gr_gm20b_get_max_fbps_count(struct gk20a *g) | |||
1126 | void gr_gm20b_init_cyclestats(struct gk20a *g) | 1126 | void gr_gm20b_init_cyclestats(struct gk20a *g) |
1127 | { | 1127 | { |
1128 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 1128 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
1129 | g->gpu_characteristics.flags |= | 1129 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, true); |
1130 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; | 1130 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT, true); |
1131 | g->gpu_characteristics.flags |= | ||
1132 | NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS_SNAPSHOT; | ||
1133 | g->gpu_characteristics.max_css_buffer_size = 0xffffffff; | 1131 | g->gpu_characteristics.max_css_buffer_size = 0xffffffff; |
1134 | #else | 1132 | #else |
1135 | (void)g; | 1133 | (void)g; |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 1e81796e..c5b62948 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -189,26 +189,24 @@ static int gp106_get_litter_value(struct gk20a *g, int value) | |||
189 | 189 | ||
190 | static int gp106_init_gpu_characteristics(struct gk20a *g) | 190 | static int gp106_init_gpu_characteristics(struct gk20a *g) |
191 | { | 191 | { |
192 | struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics; | ||
193 | |||
194 | int err; | 192 | int err; |
195 | 193 | ||
196 | err = gk20a_init_gpu_characteristics(g); | 194 | err = gk20a_init_gpu_characteristics(g); |
197 | if (err) | 195 | if (err) |
198 | return err; | 196 | return err; |
199 | 197 | ||
200 | gpu->flags |= NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE | | 198 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, true); |
201 | NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT | | 199 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, true); |
202 | NVGPU_GPU_FLAGS_SUPPORT_GET_POWER | | 200 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, true); |
203 | NVGPU_GPU_FLAGS_SUPPORT_GET_TEMPERATURE | | 201 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_TEMPERATURE, true); |
204 | NVGPU_GPU_FLAGS_SUPPORT_DEVICE_EVENTS | | 202 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_DEVICE_EVENTS, true); |
205 | NVGPU_GPU_FLAGS_SUPPORT_SET_THERM_ALERT_LIMIT; | 203 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT, true); |
206 | 204 | ||
207 | /* WAR for missing INA3221 on HW2.5 RevA */ | 205 | /* WAR for missing INA3221 on HW2.5 RevA */ |
208 | if (g->power_sensor_missing) { | 206 | if (g->power_sensor_missing) { |
209 | gpu->flags &= ~(NVGPU_GPU_FLAGS_SUPPORT_GET_VOLTAGE | | 207 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_VOLTAGE, false); |
210 | NVGPU_GPU_FLAGS_SUPPORT_GET_CURRENT | | 208 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_CURRENT, false); |
211 | NVGPU_GPU_FLAGS_SUPPORT_GET_POWER); | 209 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_GET_POWER, false); |
212 | } | 210 | } |
213 | 211 | ||
214 | return 0; | 212 | return 0; |
diff --git a/drivers/gpu/nvgpu/gp10b/gp10b.c b/drivers/gpu/nvgpu/gp10b/gp10b.c index 769d6ef3..51dc4301 100644 --- a/drivers/gpu/nvgpu/gp10b/gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gp10b.c | |||
@@ -24,14 +24,15 @@ | |||
24 | 24 | ||
25 | #include "gk20a/gk20a.h" | 25 | #include "gk20a/gk20a.h" |
26 | 26 | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
27 | #include "gp10b.h" | 29 | #include "gp10b.h" |
28 | 30 | ||
29 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | 31 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> |
30 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> | 32 | #include <nvgpu/hw/gp10b/hw_gr_gp10b.h> |
31 | 33 | ||
32 | static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | 34 | static void gp10b_detect_ecc_enabled_units(struct gk20a *g) |
33 | { | 35 | { |
34 | u64 ecc_enabled_units = 0; | ||
35 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); | 36 | u32 opt_ecc_en = gk20a_readl(g, fuse_opt_ecc_en_r()); |
36 | u32 opt_feature_fuses_override_disable = | 37 | u32 opt_feature_fuses_override_disable = |
37 | gk20a_readl(g, | 38 | gk20a_readl(g, |
@@ -41,23 +42,25 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
41 | gr_fecs_feature_override_ecc_r()); | 42 | gr_fecs_feature_override_ecc_r()); |
42 | 43 | ||
43 | if (opt_feature_fuses_override_disable) { | 44 | if (opt_feature_fuses_override_disable) { |
44 | if (opt_ecc_en) | 45 | if (opt_ecc_en) { |
45 | ecc_enabled_units = NVGPU_GPU_FLAGS_ALL_ECC_ENABLED; | 46 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_LRF, true); |
46 | else | 47 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_SM_SHM, true); |
47 | ecc_enabled_units = 0; | 48 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_TEX, true); |
49 | __nvgpu_set_enabled(g, NVGPU_ECC_ENABLED_LTC, true); | ||
50 | } | ||
48 | } else { | 51 | } else { |
49 | /* SM LRF */ | 52 | /* SM LRF */ |
50 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( | 53 | if (gr_fecs_feature_override_ecc_sm_lrf_override_v( |
51 | fecs_feature_override_ecc)) { | 54 | fecs_feature_override_ecc)) { |
52 | if (gr_fecs_feature_override_ecc_sm_lrf_v( | 55 | if (gr_fecs_feature_override_ecc_sm_lrf_v( |
53 | fecs_feature_override_ecc)) { | 56 | fecs_feature_override_ecc)) { |
54 | ecc_enabled_units |= | 57 | __nvgpu_set_enabled(g, |
55 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; | 58 | NVGPU_ECC_ENABLED_SM_LRF, true); |
56 | } | 59 | } |
57 | } else { | 60 | } else { |
58 | if (opt_ecc_en) { | 61 | if (opt_ecc_en) { |
59 | ecc_enabled_units |= | 62 | __nvgpu_set_enabled(g, |
60 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_LRF; | 63 | NVGPU_ECC_ENABLED_SM_LRF, true); |
61 | } | 64 | } |
62 | } | 65 | } |
63 | 66 | ||
@@ -66,13 +69,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
66 | fecs_feature_override_ecc)) { | 69 | fecs_feature_override_ecc)) { |
67 | if (gr_fecs_feature_override_ecc_sm_shm_v( | 70 | if (gr_fecs_feature_override_ecc_sm_shm_v( |
68 | fecs_feature_override_ecc)) { | 71 | fecs_feature_override_ecc)) { |
69 | ecc_enabled_units |= | 72 | __nvgpu_set_enabled(g, |
70 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; | 73 | NVGPU_ECC_ENABLED_SM_SHM, true); |
71 | } | 74 | } |
72 | } else { | 75 | } else { |
73 | if (opt_ecc_en) { | 76 | if (opt_ecc_en) { |
74 | ecc_enabled_units |= | 77 | __nvgpu_set_enabled(g, |
75 | NVGPU_GPU_FLAGS_ECC_ENABLED_SM_SHM; | 78 | NVGPU_ECC_ENABLED_SM_SHM, true); |
76 | } | 79 | } |
77 | } | 80 | } |
78 | 81 | ||
@@ -81,13 +84,13 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
81 | fecs_feature_override_ecc)) { | 84 | fecs_feature_override_ecc)) { |
82 | if (gr_fecs_feature_override_ecc_tex_v( | 85 | if (gr_fecs_feature_override_ecc_tex_v( |
83 | fecs_feature_override_ecc)) { | 86 | fecs_feature_override_ecc)) { |
84 | ecc_enabled_units |= | 87 | __nvgpu_set_enabled(g, |
85 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; | 88 | NVGPU_ECC_ENABLED_TEX, true); |
86 | } | 89 | } |
87 | } else { | 90 | } else { |
88 | if (opt_ecc_en) { | 91 | if (opt_ecc_en) { |
89 | ecc_enabled_units |= | 92 | __nvgpu_set_enabled(g, |
90 | NVGPU_GPU_FLAGS_ECC_ENABLED_TEX; | 93 | NVGPU_ECC_ENABLED_TEX, true); |
91 | } | 94 | } |
92 | } | 95 | } |
93 | 96 | ||
@@ -96,25 +99,22 @@ static u64 gp10b_detect_ecc_enabled_units(struct gk20a *g) | |||
96 | fecs_feature_override_ecc)) { | 99 | fecs_feature_override_ecc)) { |
97 | if (gr_fecs_feature_override_ecc_ltc_v( | 100 | if (gr_fecs_feature_override_ecc_ltc_v( |
98 | fecs_feature_override_ecc)) { | 101 | fecs_feature_override_ecc)) { |
99 | ecc_enabled_units |= | 102 | __nvgpu_set_enabled(g, |
100 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; | 103 | NVGPU_ECC_ENABLED_LTC, true); |
101 | } | 104 | } |
102 | } else { | 105 | } else { |
103 | if (opt_ecc_en) { | 106 | if (opt_ecc_en) { |
104 | ecc_enabled_units |= | 107 | __nvgpu_set_enabled(g, |
105 | NVGPU_GPU_FLAGS_ECC_ENABLED_LTC; | 108 | NVGPU_ECC_ENABLED_LTC, true); |
106 | } | 109 | } |
107 | } | 110 | } |
108 | } | 111 | } |
109 | |||
110 | return ecc_enabled_units; | ||
111 | } | 112 | } |
112 | 113 | ||
113 | int gp10b_init_gpu_characteristics(struct gk20a *g) | 114 | int gp10b_init_gpu_characteristics(struct gk20a *g) |
114 | { | 115 | { |
115 | gk20a_init_gpu_characteristics(g); | 116 | gk20a_init_gpu_characteristics(g); |
116 | g->gpu_characteristics.flags |= gp10b_detect_ecc_enabled_units(g); | 117 | gp10b_detect_ecc_enabled_units(g); |
117 | g->gpu_characteristics.flags |= | 118 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, true); |
118 | NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST; | ||
119 | return 0; | 119 | return 0; |
120 | } | 120 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index a01cfbfa..a6d72907 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <nvgpu/bug.h> | 32 | #include <nvgpu/bug.h> |
33 | #include <nvgpu/debug.h> | 33 | #include <nvgpu/debug.h> |
34 | #include <nvgpu/fuse.h> | 34 | #include <nvgpu/fuse.h> |
35 | #include <nvgpu/enabled.h> | ||
35 | 36 | ||
36 | #include "gk20a/gk20a.h" | 37 | #include "gk20a/gk20a.h" |
37 | #include "gk20a/gr_gk20a.h" | 38 | #include "gk20a/gr_gk20a.h" |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h index 8c0bb9d3..87449ccc 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h +++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h | |||
@@ -34,6 +34,18 @@ struct gk20a; | |||
34 | #define NVGPU_IS_FMODEL 1 | 34 | #define NVGPU_IS_FMODEL 1 |
35 | #define NVGPU_DRIVER_IS_DYING 2 | 35 | #define NVGPU_DRIVER_IS_DYING 2 |
36 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 | 36 | #define NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP 3 |
37 | |||
38 | /* | ||
39 | * ECC flags | ||
40 | */ | ||
41 | /* SM LRF ECC is enabled */ | ||
42 | #define NVGPU_ECC_ENABLED_SM_LRF 8 | ||
43 | /* SM SHM ECC is enabled */ | ||
44 | #define NVGPU_ECC_ENABLED_SM_SHM 9 | ||
45 | /* TEX ECC is enabled */ | ||
46 | #define NVGPU_ECC_ENABLED_TEX 10 | ||
47 | /* L2 ECC is enabled */ | ||
48 | #define NVGPU_ECC_ENABLED_LTC 11 | ||
37 | /* | 49 | /* |
38 | * MM flags. | 50 | * MM flags. |
39 | */ | 51 | */ |
@@ -44,13 +56,47 @@ struct gk20a; | |||
44 | #define NVGPU_MM_UNIFIED_MEMORY 18 | 56 | #define NVGPU_MM_UNIFIED_MEMORY 18 |
45 | /* kernel mode ce vidmem clearing channels need to be in a tsg */ | 57 | /* kernel mode ce vidmem clearing channels need to be in a tsg */ |
46 | #define NVGPU_MM_CE_TSG_REQUIRED 19 | 58 | #define NVGPU_MM_CE_TSG_REQUIRED 19 |
59 | /* User-space managed address spaces support */ | ||
60 | #define NVGPU_SUPPORT_USERSPACE_MANAGED_AS 20 | ||
61 | /* IO coherence support is available */ | ||
62 | #define NVGPU_SUPPORT_IO_COHERENCE 21 | ||
63 | /* MAP_BUFFER_EX with partial mappings */ | ||
64 | #define NVGPU_SUPPORT_PARTIAL_MAPPINGS 22 | ||
65 | /* MAP_BUFFER_EX with sparse allocations */ | ||
66 | #define NVGPU_SUPPORT_SPARSE_ALLOCS 23 | ||
67 | /* Direct PTE kind control is supported (map_buffer_ex) */ | ||
68 | #define NVGPU_SUPPORT_MAP_DIRECT_KIND_CTRL 24 | ||
69 | |||
70 | /* | ||
71 | * Host flags | ||
72 | */ | ||
73 | #define NVGPU_HAS_SYNCPOINTS 30 | ||
74 | /* sync fence FDs are available in, e.g., submit_gpfifo */ | ||
75 | #define NVGPU_SUPPORT_SYNC_FENCE_FDS 31 | ||
76 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS is available */ | ||
77 | #define NVGPU_SUPPORT_CYCLE_STATS 32 | ||
78 | /* NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT is available */ | ||
79 | #define NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT 33 | ||
80 | /* Both gpu driver and device support TSG */ | ||
81 | #define NVGPU_SUPPORT_TSG 33 | ||
82 | /* Fast deterministic submits with no job tracking are supported */ | ||
83 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_NO_JOBTRACKING 34 | ||
84 | /* Deterministic submits are supported even with job tracking */ | ||
85 | #define NVGPU_SUPPORT_DETERMINISTIC_SUBMIT_FULL 35 | ||
86 | /* NVGPU_SUBMIT_GPFIFO_FLAGS_RESCHEDULE_RUNLIST is available */ | ||
87 | #define NVGPU_SUPPORT_RESCHEDULE_RUNLIST 36 | ||
88 | |||
89 | /* NVGPU_GPU_IOCTL_GET_EVENT_FD is available */ | ||
90 | #define NVGPU_SUPPORT_DEVICE_EVENTS 37 | ||
91 | /* FECS context switch tracing is available */ | ||
92 | #define NVGPU_SUPPORT_FECS_CTXSW_TRACE 38 | ||
47 | 93 | ||
48 | /* | 94 | /* |
49 | * Security flags | 95 | * Security flags |
50 | */ | 96 | */ |
51 | 97 | ||
52 | #define NVGPU_SEC_SECUREGPCCS 32 | 98 | #define NVGPU_SEC_SECUREGPCCS 40 |
53 | #define NVGPU_SEC_PRIVSECURITY 33 | 99 | #define NVGPU_SEC_PRIVSECURITY 41 |
54 | 100 | ||
55 | /* | 101 | /* |
56 | * PMU flags. | 102 | * PMU flags. |
@@ -63,9 +109,21 @@ struct gk20a; | |||
63 | #define NVGPU_GPU_CAN_BLCG 52 | 109 | #define NVGPU_GPU_CAN_BLCG 52 |
64 | #define NVGPU_GPU_CAN_SLCG 53 | 110 | #define NVGPU_GPU_CAN_SLCG 53 |
65 | #define NVGPU_GPU_CAN_ELCG 54 | 111 | #define NVGPU_GPU_CAN_ELCG 54 |
112 | /* Clock control support */ | ||
113 | #define NVGPU_SUPPORT_CLOCK_CONTROLS 55 | ||
114 | /* NVGPU_GPU_IOCTL_GET_VOLTAGE is available */ | ||
115 | #define NVGPU_SUPPORT_GET_VOLTAGE 56 | ||
116 | /* NVGPU_GPU_IOCTL_GET_CURRENT is available */ | ||
117 | #define NVGPU_SUPPORT_GET_CURRENT 57 | ||
118 | /* NVGPU_GPU_IOCTL_GET_POWER is available */ | ||
119 | #define NVGPU_SUPPORT_GET_POWER 58 | ||
120 | /* NVGPU_GPU_IOCTL_GET_TEMPERATURE is available */ | ||
121 | #define NVGPU_SUPPORT_GET_TEMPERATURE 59 | ||
122 | /* NVGPU_GPU_IOCTL_SET_THERM_ALERT_LIMIT is available */ | ||
123 | #define NVGPU_SUPPORT_SET_THERM_ALERT_LIMIT 60 | ||
66 | 124 | ||
67 | /* whether to run PREOS binary on dGPUs */ | 125 | /* whether to run PREOS binary on dGPUs */ |
68 | #define NVGPU_PMU_RUN_PREOS 52 | 126 | #define NVGPU_PMU_RUN_PREOS 61 |
69 | 127 | ||
70 | /* | 128 | /* |
71 | * Must be greater than the largest bit offset in the above list. | 129 | * Must be greater than the largest bit offset in the above list. |
diff --git a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c index 762cc10a..72f2ae8b 100644 --- a/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fecs_trace_vgpu.c | |||
@@ -26,6 +26,7 @@ | |||
26 | 26 | ||
27 | #include <nvgpu/kmem.h> | 27 | #include <nvgpu/kmem.h> |
28 | #include <nvgpu/bug.h> | 28 | #include <nvgpu/bug.h> |
29 | #include <nvgpu/enabled.h> | ||
29 | 30 | ||
30 | #include "gk20a/gk20a.h" | 31 | #include "gk20a/gk20a.h" |
31 | #include "gk20a/ctxsw_trace_gk20a.h" | 32 | #include "gk20a/ctxsw_trace_gk20a.h" |
@@ -63,8 +64,7 @@ int vgpu_fecs_trace_init(struct gk20a *g) | |||
63 | dev_info(dev_from_gk20a(g), "does not support fecs trace\n"); | 64 | dev_info(dev_from_gk20a(g), "does not support fecs trace\n"); |
64 | goto fail; | 65 | goto fail; |
65 | } | 66 | } |
66 | g->gpu_characteristics.flags |= | 67 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_FECS_CTXSW_TRACE, true); |
67 | NVGPU_GPU_FLAGS_SUPPORT_FECS_CTXSW_TRACE; | ||
68 | 68 | ||
69 | hv_np = args.np; | 69 | hv_np = args.np; |
70 | mempool = args.args[0]; | 70 | mempool = args.args[0]; |
diff --git a/drivers/gpu/nvgpu/vgpu/vgpu.c b/drivers/gpu/nvgpu/vgpu/vgpu.c index 84034b38..f0f05637 100644 --- a/drivers/gpu/nvgpu/vgpu/vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/vgpu.c | |||
@@ -370,10 +370,8 @@ int vgpu_init_gpu_characteristics(struct gk20a *g) | |||
370 | g->gpu_characteristics.map_buffer_batch_limit = 0; | 370 | g->gpu_characteristics.map_buffer_batch_limit = 0; |
371 | 371 | ||
372 | /* features vgpu does not support */ | 372 | /* features vgpu does not support */ |
373 | g->gpu_characteristics.flags &= ~NVGPU_GPU_FLAGS_SUPPORT_CYCLE_STATS; | 373 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_CYCLE_STATS, false); |
374 | g->gpu_characteristics.flags &= ~NVGPU_GPU_FLAGS_SUPPORT_MAP_COMPBITS; | 374 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_RESCHEDULE_RUNLIST, false); |
375 | g->gpu_characteristics.flags &= | ||
376 | ~NVGPU_GPU_FLAGS_SUPPORT_RESCHEDULE_RUNLIST; | ||
377 | 375 | ||
378 | return 0; | 376 | return 0; |
379 | } | 377 | } |