diff options
author | Seema Khowala <seemaj@nvidia.com> | 2018-12-27 22:23:06 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-03-18 14:30:16 -0400 |
commit | e00804594b83781bc9f7c17ac68cd9c5dd30953c (patch) | |
tree | f687d4da54c3b2afc867b8fcdde12bf8489f95f3 | |
parent | 0c47ce7d72e4c95ca293a222e2462f52683838a3 (diff) |
gpu: nvgpu: remove gk20a_is_channel_marked_as_tsg
Use tsg_gk20a_from_ch to get tsg pointer for tsgid of a channel. For
invalid tsgid, tsg pointer will be NULL
Bug 2092051
Bug 2429295
Bug 2484211
Change-Id: I82cd6a2dc5fab4acb147202af667ca97a2842a73
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2006722
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
(cherry picked from commit 13f37f9c70b9ae2e0d179830cded93a0a6f86494
in dev-kernel)
Reviewed-on: https://git-master.nvidia.com/r/2025507
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gv11b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/channel.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/fifo/tsg.c | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/tsg.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gr_vgpu.c | 6 |
8 files changed, 49 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c index 30bf17f8..b98d1c41 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c | |||
@@ -839,6 +839,7 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
839 | int err = 0; | 839 | int err = 0; |
840 | u32 id = FIFO_INVAL_TSG_ID; | 840 | u32 id = FIFO_INVAL_TSG_ID; |
841 | unsigned int rc_type = RC_TYPE_NO_RC; | 841 | unsigned int rc_type = RC_TYPE_NO_RC; |
842 | struct tsg_gk20a *tsg = NULL; | ||
842 | 843 | ||
843 | if (!mmfault->valid) { | 844 | if (!mmfault->valid) { |
844 | return; | 845 | return; |
@@ -912,14 +913,17 @@ static void gv11b_fb_handle_mmu_fault_common(struct gk20a *g, | |||
912 | mmfault->refch->mmu_nack_handled = true; | 913 | mmfault->refch->mmu_nack_handled = true; |
913 | } | 914 | } |
914 | 915 | ||
915 | rc_type = RC_TYPE_MMU_FAULT; | 916 | tsg = tsg_gk20a_from_ch(mmfault->refch); |
916 | if (gk20a_is_channel_marked_as_tsg(mmfault->refch)) { | 917 | if (tsg != NULL) { |
917 | id = mmfault->refch->tsgid; | 918 | id = mmfault->refch->tsgid; |
918 | if (id != FIFO_INVAL_TSG_ID) { | 919 | id_type = ID_TYPE_TSG; |
919 | id_type = ID_TYPE_TSG; | 920 | rc_type = RC_TYPE_MMU_FAULT; |
920 | } | ||
921 | } else { | 921 | } else { |
922 | nvgpu_err(g, "bare channels not supported"); | 922 | nvgpu_err(g, "chid: %d is referenceable but " |
923 | "not bound to tsg", | ||
924 | mmfault->refch->chid); | ||
925 | id_type = ID_TYPE_CHANNEL; | ||
926 | rc_type = RC_TYPE_NO_RC; | ||
923 | } | 927 | } |
924 | } | 928 | } |
925 | 929 | ||
diff --git a/drivers/gpu/nvgpu/common/fifo/channel.c b/drivers/gpu/nvgpu/common/fifo/channel.c index 4b76dcdd..d30b8ded 100644 --- a/drivers/gpu/nvgpu/common/fifo/channel.c +++ b/drivers/gpu/nvgpu/common/fifo/channel.c | |||
@@ -326,7 +326,12 @@ static void gk20a_free_channel(struct channel_gk20a *ch, bool force) | |||
326 | */ | 326 | */ |
327 | if (!nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) { | 327 | if (!nvgpu_is_enabled(g, NVGPU_DRIVER_IS_DYING)) { |
328 | /* abort channel and remove from runlist */ | 328 | /* abort channel and remove from runlist */ |
329 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 329 | if (tsg_gk20a_from_ch(ch) != NULL) { |
330 | /* Between tsg is not null and unbind_channel call, | ||
331 | * ioctl cannot be called anymore because user doesn't | ||
332 | * have an open channel fd anymore to use for the unbind | ||
333 | * ioctl. | ||
334 | */ | ||
330 | err = gk20a_tsg_unbind_channel(ch); | 335 | err = gk20a_tsg_unbind_channel(ch); |
331 | if (err) { | 336 | if (err) { |
332 | nvgpu_err(g, | 337 | nvgpu_err(g, |
@@ -2264,7 +2269,7 @@ int gk20a_init_channel_support(struct gk20a *g, u32 chid) | |||
2264 | if (err) { | 2269 | if (err) { |
2265 | goto fail_6; | 2270 | goto fail_6; |
2266 | } | 2271 | } |
2267 | 2272 | nvgpu_init_list_node(&c->ch_entry); | |
2268 | nvgpu_list_add(&c->free_chs, &g->fifo.free_chs); | 2273 | nvgpu_list_add(&c->free_chs, &g->fifo.free_chs); |
2269 | 2274 | ||
2270 | return 0; | 2275 | return 0; |
@@ -2403,10 +2408,9 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events) | |||
2403 | nvgpu_cond_broadcast_interruptible( | 2408 | nvgpu_cond_broadcast_interruptible( |
2404 | &c->semaphore_wq); | 2409 | &c->semaphore_wq); |
2405 | if (post_events) { | 2410 | if (post_events) { |
2406 | if (gk20a_is_channel_marked_as_tsg(c)) { | 2411 | struct tsg_gk20a *tsg = |
2407 | struct tsg_gk20a *tsg = | 2412 | tsg_gk20a_from_ch(c); |
2408 | &g->fifo.tsg[c->tsgid]; | 2413 | if (tsg != NULL) { |
2409 | |||
2410 | g->ops.fifo.post_event_id(tsg, | 2414 | g->ops.fifo.post_event_id(tsg, |
2411 | NVGPU_EVENT_ID_BLOCKING_SYNC); | 2415 | NVGPU_EVENT_ID_BLOCKING_SYNC); |
2412 | } | 2416 | } |
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c index 9790553f..e6dfbae6 100644 --- a/drivers/gpu/nvgpu/common/fifo/tsg.c +++ b/drivers/gpu/nvgpu/common/fifo/tsg.c | |||
@@ -28,11 +28,6 @@ | |||
28 | #include <nvgpu/tsg.h> | 28 | #include <nvgpu/tsg.h> |
29 | #include <nvgpu/gk20a.h> | 29 | #include <nvgpu/gk20a.h> |
30 | 30 | ||
31 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch) | ||
32 | { | ||
33 | return !(ch->tsgid == NVGPU_INVALID_TSG_ID); | ||
34 | } | ||
35 | |||
36 | int gk20a_enable_tsg(struct tsg_gk20a *tsg) | 31 | int gk20a_enable_tsg(struct tsg_gk20a *tsg) |
37 | { | 32 | { |
38 | struct gk20a *g = tsg->g; | 33 | struct gk20a *g = tsg->g; |
@@ -116,7 +111,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
116 | nvgpu_log_fn(g, " "); | 111 | nvgpu_log_fn(g, " "); |
117 | 112 | ||
118 | /* check if channel is already bound to some TSG */ | 113 | /* check if channel is already bound to some TSG */ |
119 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 114 | if (tsg_gk20a_from_ch(ch) != NULL) { |
120 | return -EINVAL; | 115 | return -EINVAL; |
121 | } | 116 | } |
122 | 117 | ||
@@ -125,7 +120,6 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
125 | return -EINVAL; | 120 | return -EINVAL; |
126 | } | 121 | } |
127 | 122 | ||
128 | ch->tsgid = tsg->tsgid; | ||
129 | 123 | ||
130 | /* all the channel part of TSG should need to be same runlist_id */ | 124 | /* all the channel part of TSG should need to be same runlist_id */ |
131 | if (tsg->runlist_id == FIFO_INVAL_TSG_ID) { | 125 | if (tsg->runlist_id == FIFO_INVAL_TSG_ID) { |
@@ -139,6 +133,7 @@ int gk20a_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
139 | 133 | ||
140 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 134 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
141 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); | 135 | nvgpu_list_add_tail(&ch->ch_entry, &tsg->ch_list); |
136 | ch->tsgid = tsg->tsgid; | ||
142 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 137 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
143 | 138 | ||
144 | nvgpu_ref_get(&tsg->refcount); | 139 | nvgpu_ref_get(&tsg->refcount); |
@@ -172,14 +167,13 @@ int gk20a_tsg_unbind_channel(struct channel_gk20a *ch) | |||
172 | 167 | ||
173 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 168 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
174 | nvgpu_list_del(&ch->ch_entry); | 169 | nvgpu_list_del(&ch->ch_entry); |
170 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
175 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 171 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
176 | } | 172 | } |
173 | nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d", | ||
174 | tsg->tsgid, ch->chid); | ||
177 | 175 | ||
178 | nvgpu_ref_put(&tsg->refcount, gk20a_tsg_release); | 176 | nvgpu_ref_put(&tsg->refcount, gk20a_tsg_release); |
179 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
180 | |||
181 | nvgpu_log(g, gpu_dbg_fn, "UNBIND tsg:%d channel:%d\n", | ||
182 | tsg->tsgid, ch->chid); | ||
183 | 177 | ||
184 | return 0; | 178 | return 0; |
185 | } | 179 | } |
@@ -395,13 +389,17 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
395 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) | 389 | struct tsg_gk20a *tsg_gk20a_from_ch(struct channel_gk20a *ch) |
396 | { | 390 | { |
397 | struct tsg_gk20a *tsg = NULL; | 391 | struct tsg_gk20a *tsg = NULL; |
392 | u32 tsgid = ch->tsgid; | ||
398 | 393 | ||
399 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 394 | if (tsgid != NVGPU_INVALID_TSG_ID) { |
400 | struct gk20a *g = ch->g; | 395 | struct gk20a *g = ch->g; |
401 | struct fifo_gk20a *f = &g->fifo; | 396 | struct fifo_gk20a *f = &g->fifo; |
402 | tsg = &f->tsg[ch->tsgid]; | ||
403 | } | ||
404 | 397 | ||
398 | tsg = &f->tsg[tsgid]; | ||
399 | } else { | ||
400 | nvgpu_log(ch->g, gpu_dbg_fn, "tsgid is invalid for chid: %d", | ||
401 | ch->chid); | ||
402 | } | ||
405 | return tsg; | 403 | return tsg; |
406 | } | 404 | } |
407 | 405 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index f12c78f8..f4b96b7a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2154,11 +2154,15 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch) | |||
2154 | int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) | 2154 | int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) |
2155 | { | 2155 | { |
2156 | struct gk20a *g = ch->g; | 2156 | struct gk20a *g = ch->g; |
2157 | struct fifo_gk20a *f = &g->fifo; | 2157 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); |
2158 | struct tsg_gk20a *tsg = &f->tsg[ch->tsgid]; | ||
2159 | int err; | 2158 | int err; |
2160 | bool tsg_timedout = false; | 2159 | bool tsg_timedout = false; |
2161 | 2160 | ||
2161 | if (tsg == NULL) { | ||
2162 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); | ||
2163 | return 0; | ||
2164 | } | ||
2165 | |||
2162 | /* If one channel in TSG times out, we disable all channels */ | 2166 | /* If one channel in TSG times out, we disable all channels */ |
2163 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 2167 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
2164 | tsg_timedout = gk20a_channel_check_timedout(ch); | 2168 | tsg_timedout = gk20a_channel_check_timedout(ch); |
@@ -2188,6 +2192,7 @@ int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) | |||
2188 | /* Remove channel from TSG and re-enable rest of the channels */ | 2192 | /* Remove channel from TSG and re-enable rest of the channels */ |
2189 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 2193 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
2190 | nvgpu_list_del(&ch->ch_entry); | 2194 | nvgpu_list_del(&ch->ch_entry); |
2195 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
2191 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 2196 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
2192 | 2197 | ||
2193 | /* | 2198 | /* |
@@ -3485,9 +3490,7 @@ int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3485 | Otherwise, keep active list untouched for suspend/resume. */ | 3490 | Otherwise, keep active list untouched for suspend/resume. */ |
3486 | if (chid != FIFO_INVAL_CHANNEL_ID) { | 3491 | if (chid != FIFO_INVAL_CHANNEL_ID) { |
3487 | ch = &f->channel[chid]; | 3492 | ch = &f->channel[chid]; |
3488 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 3493 | tsg = tsg_gk20a_from_ch(ch); |
3489 | tsg = &f->tsg[ch->tsgid]; | ||
3490 | } | ||
3491 | 3494 | ||
3492 | if (add) { | 3495 | if (add) { |
3493 | if (test_and_set_bit(chid, | 3496 | if (test_and_set_bit(chid, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 46cbfd8c..9e4d3c37 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8077,6 +8077,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
8077 | struct gk20a *g = ch->g; | 8077 | struct gk20a *g = ch->g; |
8078 | struct channel_gk20a *curr_ch; | 8078 | struct channel_gk20a *curr_ch; |
8079 | bool ret = false; | 8079 | bool ret = false; |
8080 | struct tsg_gk20a *tsg; | ||
8080 | 8081 | ||
8081 | curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r()); | 8082 | curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r()); |
8082 | 8083 | ||
@@ -8108,7 +8109,8 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
8108 | ret = true; | 8109 | ret = true; |
8109 | } | 8110 | } |
8110 | 8111 | ||
8111 | if (gk20a_is_channel_marked_as_tsg(ch) && (ch->tsgid == curr_gr_tsgid)) { | 8112 | tsg = tsg_gk20a_from_ch(ch); |
8113 | if ((tsg != NULL) && (tsg->tsgid == curr_gr_tsgid)) { | ||
8112 | ret = true; | 8114 | ret = true; |
8113 | } | 8115 | } |
8114 | 8116 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h index e87be90d..212fb77c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h | |||
@@ -32,7 +32,6 @@ | |||
32 | 32 | ||
33 | struct channel_gk20a; | 33 | struct channel_gk20a; |
34 | 34 | ||
35 | bool gk20a_is_channel_marked_as_tsg(struct channel_gk20a *ch); | ||
36 | struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid); | 35 | struct tsg_gk20a *gk20a_tsg_open(struct gk20a *g, pid_t pid); |
37 | void gk20a_tsg_release(struct nvgpu_ref *ref); | 36 | void gk20a_tsg_release(struct nvgpu_ref *ref); |
38 | 37 | ||
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 0dc163e2..adf40d5d 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -1667,6 +1667,7 @@ static int nvgpu_profiler_reserve_acquire(struct dbg_session_gk20a *dbg_s, | |||
1667 | struct gk20a *g = dbg_s->g; | 1667 | struct gk20a *g = dbg_s->g; |
1668 | struct dbg_profiler_object_data *prof_obj, *my_prof_obj; | 1668 | struct dbg_profiler_object_data *prof_obj, *my_prof_obj; |
1669 | int err = 0; | 1669 | int err = 0; |
1670 | struct tsg_gk20a *tsg; | ||
1670 | 1671 | ||
1671 | nvgpu_log_fn(g, "%s profiler_handle = %x", g->name, profiler_handle); | 1672 | nvgpu_log_fn(g, "%s profiler_handle = %x", g->name, profiler_handle); |
1672 | 1673 | ||
@@ -1709,11 +1710,11 @@ static int nvgpu_profiler_reserve_acquire(struct dbg_session_gk20a *dbg_s, | |||
1709 | nvgpu_err(g, | 1710 | nvgpu_err(g, |
1710 | "per-ctxt reserve: global reservation in effect"); | 1711 | "per-ctxt reserve: global reservation in effect"); |
1711 | err = -EBUSY; | 1712 | err = -EBUSY; |
1712 | } else if (gk20a_is_channel_marked_as_tsg(my_prof_obj->ch)) { | 1713 | } else if ((tsg = tsg_gk20a_from_ch(my_prof_obj->ch)) != NULL) { |
1713 | /* TSG: check that another channel in the TSG | 1714 | /* TSG: check that another channel in the TSG |
1714 | * doesn't already have the reservation | 1715 | * doesn't already have the reservation |
1715 | */ | 1716 | */ |
1716 | u32 my_tsgid = my_prof_obj->ch->tsgid; | 1717 | u32 my_tsgid = tsg->tsgid; |
1717 | 1718 | ||
1718 | nvgpu_list_for_each_entry(prof_obj, &g->profiler_objects, | 1719 | nvgpu_list_for_each_entry(prof_obj, &g->profiler_objects, |
1719 | dbg_profiler_object_data, prof_obj_entry) { | 1720 | dbg_profiler_object_data, prof_obj_entry) { |
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c index 6a86c9a0..e3b1888e 100644 --- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c | |||
@@ -501,7 +501,6 @@ static int vgpu_gr_tsg_bind_gr_ctx(struct tsg_gk20a *tsg) | |||
501 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | 501 | int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) |
502 | { | 502 | { |
503 | struct gk20a *g = c->g; | 503 | struct gk20a *g = c->g; |
504 | struct fifo_gk20a *f = &g->fifo; | ||
505 | struct nvgpu_gr_ctx *gr_ctx = NULL; | 504 | struct nvgpu_gr_ctx *gr_ctx = NULL; |
506 | struct tsg_gk20a *tsg = NULL; | 505 | struct tsg_gk20a *tsg = NULL; |
507 | int err = 0; | 506 | int err = 0; |
@@ -522,10 +521,11 @@ int vgpu_gr_alloc_obj_ctx(struct channel_gk20a *c, u32 class_num, u32 flags) | |||
522 | } | 521 | } |
523 | c->obj_class = class_num; | 522 | c->obj_class = class_num; |
524 | 523 | ||
525 | if (!gk20a_is_channel_marked_as_tsg(c)) | 524 | tsg = tsg_gk20a_from_ch(c); |
525 | if (tsg == NULL) { | ||
526 | return -EINVAL; | 526 | return -EINVAL; |
527 | } | ||
527 | 528 | ||
528 | tsg = &f->tsg[c->tsgid]; | ||
529 | gr_ctx = &tsg->gr_ctx; | 529 | gr_ctx = &tsg->gr_ctx; |
530 | 530 | ||
531 | if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { | 531 | if (!nvgpu_mem_is_valid(&gr_ctx->mem)) { |