gpu: nvgpu: fix some MISRA 10.3 violations

Fix MISRA 10.3 violations in mclk_gp106.c. Cleanup cases where values
were being assigned to narrower types.

Changes in mclk_gp106.c required updates to other files to resolve
errors and prevent introducing new violations.

JIRA NVGPU-647

Change-Id: Ifdb03ad41d9dbf05dbcf79494ae8565fff6ee083
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 55 insertions, 43 deletions

diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.h b/drivers/gpu/nvgpu/clk/clk_mclk.h
index a0d3fd5d..00356c98 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.h
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.h
@@ -1,5 +1,5 @@
 /*
-* Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+* Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
 *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,10 +25,10 @@
 
 #include <nvgpu/lock.h>
 
-#define GP106_MCLK_LOW_SPEED    0
-#define GP106_MCLK_MID_SPEED    1
-#define GP106_MCLK_HIGH_SPEED   2
-#define GP106_MCLK_NUM_SPEED    3
+#define GP106_MCLK_LOW_SPEED    0U
+#define GP106_MCLK_MID_SPEED    1U
+#define GP106_MCLK_HIGH_SPEED   2U
+#define GP106_MCLK_NUM_SPEED    3U
 
 enum gk20a_mclk_speed {
         gk20a_mclk_low_speed,
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index e9497ea7..dd63a105 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1653,10 +1653,10 @@ static inline bool nvgpu_is_timeouts_enabled(struct gk20a *g)
         return nvgpu_atomic_read(&g->timeouts_disabled_refcount) == 0;
 }
 
-static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
+static inline u32 gk20a_get_gr_idle_timeout(struct gk20a *g)
 {
         return nvgpu_is_timeouts_enabled(g) ?
-                g->gr_idle_timeout_default : ULONG_MAX;
+                g->gr_idle_timeout_default : UINT_MAX;
 }
 
 #define MULTICHAR_TAG(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
diff --git a/drivers/gpu/nvgpu/gp106/mclk_gp106.c b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
index 6a49e83b..b4f553ec 100644
--- a/drivers/gpu/nvgpu/gp106/mclk_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/mclk_gp106.c
@@ -39,14 +39,9 @@
 
 #define VREG_COUNT 24
 
-#define GP106_MCLK_LOW_SPEED    0
-#define GP106_MCLK_MID_SPEED    1
-#define GP106_MCLK_HIGH_SPEED   2
-#define GP106_MCLK_NUM_SPEED    3
-
-#define GP106_MEM_CONFIG_GDDR5_PG418            0
-#define GP106_MEM_CONFIG_GDDR5_PG419            1
-#define GP106_MEM_CONFIG_GDDR5_PG419_8606580012 2
+#define GP106_MEM_CONFIG_GDDR5_PG418            0U
+#define GP106_MEM_CONFIG_GDDR5_PG419            1U
+#define GP106_MEM_CONFIG_GDDR5_PG419_8606580012 2U
 
 struct memory_link_training_pattern {
         u32 regaddr;
@@ -2939,7 +2934,7 @@ static int mclk_debugfs_init(struct gk20a *g);
 
 struct memory_config {
         struct memory_link_training_pattern *pattern_ptr;
-        u32 pattern_size;
+        size_t pattern_size;
         struct {
                 u8 *addr;
                 u32 size;
@@ -2949,7 +2944,7 @@ struct memory_config {
 #undef S
 #define S(from, to, script) \
         [GP106_MCLK_##from##_SPEED][GP106_MCLK_##to##_SPEED] = \
-                { script, sizeof(script) }
+                { script, (u32)sizeof(script) }
 
 static struct memory_config mem_config[] = {
         [GP106_MEM_CONFIG_GDDR5_PG418] = {
@@ -2998,7 +2993,8 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg,
 {
         struct nv_pmu_seq_msg *msg = (struct nv_pmu_seq_msg *)_msg;
         struct nv_pmu_seq_msg_run_script *seq_msg;
-        u32 msg_status = 0;
+        int msg_status = 0;
+        bool *seq_running = (bool *)param; /* to report back completion */
 
         nvgpu_log_info(g, " ");
 
@@ -3021,7 +3017,7 @@ static void mclk_seq_pmucmdhandler(struct gk20a *g, struct pmu_msg *_msg,
         }
 
 status_update:
-        *((u32 *)param) = msg_status;
+        *seq_running = (msg_status != 0);
 }
 
 static int mclk_get_memclk_table(struct gk20a *g)
@@ -3087,8 +3083,8 @@ static int mclk_get_memclk_table(struct gk20a *g)
                         VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX);
 
                 script_ptr = nvgpu_bios_read_u32(g,
-                        memclock_table_header.script_list_ptr +
-                                script_index * sizeof(u32));
+                        (u32)(memclock_table_header.script_list_ptr +
+                                script_index * sizeof(u32)));
 
                 if (!script_ptr) {
                         continue;
@@ -3142,8 +3138,8 @@ static int mclk_get_memclk_table(struct gk20a *g)
                         VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX);
 
                 cmd_script_ptr = nvgpu_bios_read_u32(g,
-                        memclock_table_header.cmd_script_list_ptr +
-                                cmd_script_index * sizeof(u32));
+                        (u32)(memclock_table_header.cmd_script_list_ptr +
+                                cmd_script_index * sizeof(u32)));
 
                 if (!cmd_script_ptr) {
                         continue;
@@ -3268,14 +3264,14 @@ int gp106_mclk_init(struct gk20a *g)
 
         p5_info = pstate_get_clk_set_info(g,
                         CTRL_PERF_PSTATE_P5, clkwhich_mclk);
-        if (!p5_info) {
+        if (p5_info == NULL) {
                 err = -EINVAL;
                 goto fail_data_mutex;
         }
 
         p0_info = pstate_get_clk_set_info(g,
                         CTRL_PERF_PSTATE_P0, clkwhich_mclk);
-        if (!p0_info) {
+        if (p0_info == NULL) {
                 err = -EINVAL;
                 goto fail_data_mutex;
         }
@@ -3284,7 +3280,7 @@ int gp106_mclk_init(struct gk20a *g)
         mclk->p0_min = p0_info->min_mhz;
 
         mclk->vreg_buf = nvgpu_kcalloc(g, VREG_COUNT, sizeof(u32));
-        if (!mclk->vreg_buf) {
+        if (mclk->vreg_buf == NULL) {
                 nvgpu_err(g, "unable to allocate memory for VREG");
                 err = -ENOMEM;
                 goto fail_data_mutex;
@@ -3318,13 +3314,14 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
         int status = 0;
         struct memory_config *m = &mem_config[g->mem_config_idx];
 
-        u32 seq_completion_status = ~0x0;
+        bool seq_running = true;
         u8 *seq_script_ptr = NULL;
-        size_t seq_script_size = 0;
+        u32 seq_script_size = 0;
 #ifdef CONFIG_DEBUG_FS
         u64 t0, t1;
 #endif
         u32 speed;
+        u64 cmd_hdr_size;
 
         nvgpu_log_info(g, " ");
 
@@ -3357,8 +3354,14 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
         /* Fill command header with SEQ ID & size */
         memset(&cmd, 0, sizeof(cmd));
         cmd.hdr.unit_id = PMU_UNIT_SEQ;
-        cmd.hdr.size = sizeof(struct nv_pmu_seq_cmd_run_script) +
+        cmd_hdr_size = sizeof(struct nv_pmu_seq_cmd_run_script) +
                 sizeof(struct pmu_hdr);
+        if (cmd_hdr_size > U8_MAX) {
+                nvgpu_err(g, "Invalid command header size");
+                status = -EINVAL;
+                goto exit_status;
+        }
+        cmd.hdr.size = (u8)cmd_hdr_size;
 
         /* Fill RM_PMU_SEQ_CMD_RUN_SCRIPT struct */
         pseq_cmd = &cmd.run_script;
@@ -3379,24 +3382,24 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
 
         /* Read sequencer binary*/
         payload.in.buf = seq_script_ptr;
-        payload.in.size = seq_script_size;
+        payload.in.size = (u32)seq_script_size;
         payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
-        payload.in.offset = offsetof(struct nv_pmu_seq_cmd_run_script,
+        payload.in.offset = (u32)offsetof(struct nv_pmu_seq_cmd_run_script,
                         script_alloc);
 
         memset(mclk->vreg_buf, 0, (sizeof(u32) * VREG_COUNT));
 
         payload.out.buf = mclk->vreg_buf;
-        payload.out.size = (VREG_COUNT * sizeof(u32));
+        payload.out.size = (VREG_COUNT * (u32)sizeof(u32));
         payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
-        payload.out.offset = offsetof(struct nv_pmu_seq_cmd_run_script,
+        payload.out.offset = (u32)offsetof(struct nv_pmu_seq_cmd_run_script,
                         reg_alloc);
 
         /* Send command to PMU to execute sequencer script */
         status = nvgpu_pmu_cmd_post(g, (struct pmu_cmd *)&cmd, NULL, &payload,
                         PMU_COMMAND_QUEUE_LPQ,
                         mclk_seq_pmucmdhandler,
-                        &seq_completion_status, &seqdesc, ~0);
+                        &seq_running, &seqdesc, ~0UL);
         if (status) {
                 nvgpu_err(g, "unable to post seq script exec cmd for unit %x",
                         cmd.hdr.unit_id);
@@ -3404,8 +3407,8 @@ int gp106_mclk_change(struct gk20a *g, u16 val)
         }
         /* wait till sequencer script complete */
         pmu_wait_message_cond(&g->pmu, (gk20a_get_gr_idle_timeout(g)),
-                        &seq_completion_status, 0);
-        if (seq_completion_status != 0) {
+                        &seq_running, (u8)false);
+        if (seq_running) {
                 nvgpu_err(g, "seq_script update failed");
                 status = -EBUSY;
                 goto exit_status;
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 92e0165f..2fb700f0 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -2169,7 +2169,7 @@ int gr_gp10b_suspend_contexts(struct gk20a *g,
                 struct nvgpu_timeout timeout;
 
                 nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg | gpu_dbg_intr,
-                        "CILP preempt pending, waiting %lu msecs for preemption",
+                        "CILP preempt pending, waiting %u msecs for preemption",
                         gk20a_get_gr_idle_timeout(g));
 
                 tsg = tsg_gk20a_from_ch(cilp_preempt_pending_ch);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index 10b220b7..5965d177 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -596,10 +596,12 @@ struct vbios_memory_clock_base_entry_11 {
 
 /* Script Pointer Index */
 /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX         3:2*/
-#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK       0xc
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_MASK       \
+                                                        ((u8)0xc)
 #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX_SHIFT      2
 /* #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX     1:0*/
-#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK   0x3
+#define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_MASK \
+                                                        ((u8)0x3)
 #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT  0
 
 #define VBIOS_POWER_SENSORS_VERSION_2X                                      0x20
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h
index 8320721b..d4d88d4d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/types.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -60,4 +60,11 @@
 #define U32(x)  ((u32)(x))
 #define U64(x)  ((u64)(x))
 
+/* Linux uses U8_MAX instead of UCHAR_MAX. We define it here for non-Linux
+ * OSes
+ */
+#if !defined(__KERNEL__) && !defined(U8_MAX)
+#define U8_MAX ((u8)255)
+#endif
+
 #endif
diff --git a/drivers/gpu/nvgpu/pstate/pstate.h b/drivers/gpu/nvgpu/pstate/pstate.h
index 55726d55..0860b46e 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.h
+++ b/drivers/gpu/nvgpu/pstate/pstate.h
@@ -1,7 +1,7 @@
 /*
  * general p state infrastructure
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -39,8 +39,8 @@ struct gk20a;
 struct clk_set_info {
         enum nv_pmu_clk_clkwhich clkwhich;
         u32 nominal_mhz;
-        u32 min_mhz;
-        u32 max_mhz;
+        u16 min_mhz;
+        u16 max_mhz;
 };
 
 struct clk_set_info_list {