gpu: nvgpu: gv11b: update zcull and pm pointers

Update zcull and perfmon buffer pointers in context header.
For gv11b maximum 49 bits gpu va possible. But,
zcull and perfmon buffer pointers uses maximum 41 bit
va address (258 bytes aligned). To accommodate this, high pointer
registers needs to be updated in context header.

JIRA GV11B-48

Change-Id: Ibe62b6bfedd32c4f3721e4d19d96cce58ef0f366
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1291852
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>

2 files changed, 35 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 31c1a420..daadef68 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1941,6 +1941,34 @@ static void gv11b_restore_context_header(struct gk20a *g,
         gk20a_mem_wr(g, ctxheader,
                         ctxsw_prog_main_image_num_save_ops_o(), 0);
 }
+static void gr_gv11b_write_zcull_ptr(struct gk20a *g,
+                                struct mem_desc *mem, u64 gpu_va)
+{
+        u32 va_lo, va_hi;
+
+        gpu_va = gpu_va >> 8;
+        va_lo = u64_lo32(gpu_va);
+        va_hi = u64_hi32(gpu_va);
+        gk20a_mem_wr(g, mem,
+                ctxsw_prog_main_image_zcull_ptr_o(), va_lo);
+        gk20a_mem_wr(g, mem,
+                ctxsw_prog_main_image_zcull_ptr_hi_o(), va_hi);
+}
+
+
+static void gr_gv11b_write_pm_ptr(struct gk20a *g,
+                                struct mem_desc *mem, u64 gpu_va)
+{
+        u32 va_lo, va_hi;
+
+        gpu_va = gpu_va >> 8;
+        va_lo = u64_lo32(gpu_va);
+        va_hi = u64_hi32(gpu_va);
+        gk20a_mem_wr(g, mem,
+                ctxsw_prog_main_image_pm_ptr_o(), va_lo);
+        gk20a_mem_wr(g, mem,
+                ctxsw_prog_main_image_pm_ptr_hi_o(), va_hi);
+}
 
 void gv11b_init_gr(struct gpu_ops *gops)
 {
@@ -1995,5 +2023,7 @@ void gv11b_init_gr(struct gpu_ops *gops)
                         gr_gv11b_program_sm_id_numbering;
         gops->gr.commit_inst = gr_gv11b_commit_inst;
         gops->gr.restore_context_header = gv11b_restore_context_header;
+        gops->gr.write_zcull_ptr = gr_gv11b_write_zcull_ptr;
+        gops->gr.write_pm_ptr = gr_gv11b_write_pm_ptr;
 
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
index 228bf5f2..a0f40de0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_ctxsw_prog_gv11b.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -186,6 +186,10 @@ static inline u32 ctxsw_prog_main_image_zcull_ptr_hi_v_f(u32 v)
 {
         return (v & 0x1ffff) << 0;
 }
+static inline u32 ctxsw_prog_main_image_pm_ptr_hi_o(void)
+{
+        return 0x00000094;
+}
 static inline u32 ctxsw_prog_main_image_full_preemption_ptr_hi_o(void)
 {
         return 0x00000064;