gpu: nvgpu: Fix MISRA 15.6 violations

MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces,
including single statement blocks. Fix errors due to single statement
if blocks without braces by introducing the braces.

JIRA NVGPU-671

Change-Id: I8046a09fa7ffc74c3d737ba57132a0a9ae2ff195
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1797699
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Nitin Kumbhar <nkumbhar@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

17 files changed, 335 insertions, 179 deletions

diff --git a/drivers/gpu/nvgpu/common/xve/xve_gp106.c b/drivers/gpu/nvgpu/common/xve/xve_gp106.c
index 3ed02f1b..29d97843 100644
--- a/drivers/gpu/nvgpu/common/xve/xve_gp106.c
+++ b/drivers/gpu/nvgpu/common/xve/xve_gp106.c
@@ -104,15 +104,19 @@ int xve_get_speed_gp106(struct gk20a *g, u32 *xve_link_speed)
          * Can't use a switch statement becuase switch statements dont work with
          * function calls.
          */
-        if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v())
+        if (link_speed == xve_link_control_status_link_speed_link_speed_2p5_v()) {
                 real_link_speed = GPU_XVE_SPEED_2P5;
-        if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v())
+        }
+        if (link_speed == xve_link_control_status_link_speed_link_speed_5p0_v()) {
                 real_link_speed = GPU_XVE_SPEED_5P0;
-        if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v())
+        }
+        if (link_speed == xve_link_control_status_link_speed_link_speed_8p0_v()) {
                 real_link_speed = GPU_XVE_SPEED_8P0;
+        }
 
-        if (real_link_speed == 0U)
+        if (real_link_speed == 0U) {
                 return -ENODEV;
+        }
 
         *xve_link_speed = real_link_speed;
         return 0;
@@ -240,8 +244,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
                 if ((xp_pl_link_config_ltssm_status_f(pl_link_config) ==
                      xp_pl_link_config_ltssm_status_idle_v()) &&
                     (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
-                     xp_pl_link_config_ltssm_directive_normal_operations_v()))
+                     xp_pl_link_config_ltssm_directive_normal_operations_v())) {
                         break;
+                }
         } while (nvgpu_timeout_expired(&timeout) == 0);
 
         if (nvgpu_timeout_peek_expired(&timeout)) {
@@ -283,23 +288,24 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
         pl_link_config &= ~xp_pl_link_config_target_tx_width_m();
 
         /* Can't use a switch due to oddities in register definitions. */
-        if (link_width == xve_link_control_status_link_width_x1_v())
+        if (link_width == xve_link_control_status_link_width_x1_v()) {
                 pl_link_config |= xp_pl_link_config_target_tx_width_f(
                         xp_pl_link_config_target_tx_width_x1_v());
-        else if (link_width == xve_link_control_status_link_width_x2_v())
+        } else if (link_width == xve_link_control_status_link_width_x2_v()) {
                 pl_link_config |= xp_pl_link_config_target_tx_width_f(
                         xp_pl_link_config_target_tx_width_x2_v());
-        else if (link_width == xve_link_control_status_link_width_x4_v())
+        } else if (link_width == xve_link_control_status_link_width_x4_v()) {
                 pl_link_config |= xp_pl_link_config_target_tx_width_f(
                         xp_pl_link_config_target_tx_width_x4_v());
-        else if (link_width == xve_link_control_status_link_width_x8_v())
+        } else if (link_width == xve_link_control_status_link_width_x8_v()) {
                 pl_link_config |= xp_pl_link_config_target_tx_width_f(
                         xp_pl_link_config_target_tx_width_x8_v());
-        else if (link_width == xve_link_control_status_link_width_x16_v())
+        } else if (link_width == xve_link_control_status_link_width_x16_v()) {
                 pl_link_config |= xp_pl_link_config_target_tx_width_f(
                         xp_pl_link_config_target_tx_width_x16_v());
-        else
+        } else {
                 BUG();
+        }
 
         xv_sc_dbg(g, LINK_SETTINGS, "  pl_link_config = 0x%08x", pl_link_config);
         xv_sc_dbg(g, LINK_SETTINGS, "  Done");
@@ -311,8 +317,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
         do {
                 gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config);
                 if (pl_link_config ==
-                    gk20a_readl(g, xp_pl_link_config_r(0)))
+                    gk20a_readl(g, xp_pl_link_config_r(0))) {
                         break;
+                }
         } while (nvgpu_timeout_expired(&timeout) == 0);
 
         if (nvgpu_timeout_peek_expired(&timeout)) {
@@ -346,8 +353,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
                             (xp_pl_link_config_ltssm_status_f(pl_link_config) ==
                              xp_pl_link_config_ltssm_status_idle_v()) &&
                             (xp_pl_link_config_ltssm_directive_f(pl_link_config) ==
-                             xp_pl_link_config_ltssm_directive_normal_operations_v()))
+                             xp_pl_link_config_ltssm_directive_normal_operations_v())) {
                                 break;
+                        }
                 } while (nvgpu_timeout_expired(&timeout) == 0);
 
                 if (nvgpu_timeout_peek_expired(&timeout)) {
@@ -403,20 +411,21 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
 
                 link_config &= ~xp_pl_link_config_max_link_rate_m();
                 if (new_link_speed ==
-                    xve_link_control_status_link_speed_link_speed_2p5_v())
+                    xve_link_control_status_link_speed_link_speed_2p5_v()) {
                         link_config |= xp_pl_link_config_max_link_rate_f(
                                 xp_pl_link_config_max_link_rate_2500_mtps_v());
-                else if (new_link_speed ==
-                         xve_link_control_status_link_speed_link_speed_5p0_v())
+                } else if (new_link_speed ==
+                         xve_link_control_status_link_speed_link_speed_5p0_v()) {
                         link_config |= xp_pl_link_config_max_link_rate_f(
                                 xp_pl_link_config_max_link_rate_5000_mtps_v());
-                else if (new_link_speed ==
-                         xve_link_control_status_link_speed_link_speed_8p0_v())
+                } else if (new_link_speed ==
+                         xve_link_control_status_link_speed_link_speed_8p0_v()) {
                         link_config |= xp_pl_link_config_max_link_rate_f(
                                 xp_pl_link_config_max_link_rate_8000_mtps_v());
-                else
+                } else {
                         link_config |= xp_pl_link_config_max_link_rate_f(
                                 xp_pl_link_config_max_link_rate_2500_mtps_v());
+                }
 
                 gk20a_writel(g, xp_pl_link_config_r(0), link_config);
                 err_status = -ENODEV;
@@ -452,16 +461,19 @@ int xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed)
         u32 current_link_speed;
         int err;
 
-        if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0)
+        if ((next_link_speed & GPU_XVE_SPEED_MASK) == 0) {
                 return -EINVAL;
+        }
 
         err = g->ops.xve.get_speed(g, &current_link_speed);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         /* No-op. */
-        if (current_link_speed == next_link_speed)
+        if (current_link_speed == next_link_speed) {
                 return 0;
+        }
 
         return __do_xve_set_speed_gp106(g, next_link_speed);
 }
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kref.h b/drivers/gpu/nvgpu/include/nvgpu/kref.h
index 72b21ec4..2cbc07bc 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/kref.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/kref.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -66,8 +66,9 @@ static inline int nvgpu_ref_put(struct nvgpu_ref *ref,
                 void (*release)(struct nvgpu_ref *r))
 {
         if (nvgpu_atomic_sub_and_test(1, &ref->refcount)) {
-                if (release != NULL)
+                if (release != NULL) {
                         release(ref);
+                }
                 return 1;
         }
         return 0;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h
index 598e064f..3369eb20 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/ptimer.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/ptimer.h
@@ -42,10 +42,11 @@ static inline u32 ptimer_scalingfactor10x(u32 ptimer_src_freq)
 
 static inline u32 scale_ptimer(u32 timeout , u32 scale10x)
 {
-        if (((timeout*10) % scale10x) >= (scale10x/2))
+        if (((timeout*10) % scale10x) >= (scale10x/2)) {
                 return ((timeout * 10) / scale10x) + 1;
-        else
+        } else {
                 return (timeout * 10) / scale10x;
+        }
 }
 
 int nvgpu_get_timestamps_zipper(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/xve.h b/drivers/gpu/nvgpu/include/nvgpu/xve.h
index acaf441c..2d0d6982 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/xve.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/xve.h
@@ -55,8 +55,9 @@
 static inline const char *xve_speed_to_str(u32 speed)
 {
         if (!speed || !is_power_of_2(speed) ||
-            !(speed & GPU_XVE_SPEED_MASK))
+            !(speed & GPU_XVE_SPEED_MASK)) {
                 return "Unknown ???";
+        }
 
         return speed & GPU_XVE_SPEED_2P5 ? "Gen1" :
                speed & GPU_XVE_SPEED_5P0 ? "Gen2" :
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 3be8269a..a536bf9e 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -42,14 +42,16 @@ static int get_lpwr_idx_table(struct gk20a *g)
 
         lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
                 g->bios.perf_token, LOWPOWER_TABLE);
-        if (lpwr_idx_table_ptr == NULL)
+        if (lpwr_idx_table_ptr == NULL) {
                 return -EINVAL;
+        }
 
         memcpy(&header, lpwr_idx_table_ptr,
                 sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header));
 
-        if (header.entry_count >= LPWR_VBIOS_IDX_ENTRY_COUNT_MAX)
+        if (header.entry_count >= LPWR_VBIOS_IDX_ENTRY_COUNT_MAX) {
                 return -EINVAL;
+        }
 
         pidx_data->base_sampling_period = (u16)header.base_sampling_period;
 
@@ -84,8 +86,9 @@ static int get_lpwr_gr_table(struct gk20a *g)
 
         lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
                 g->bios.perf_token, LOWPOWER_GR_TABLE);
-        if (lpwr_gr_table_ptr == NULL)
+        if (lpwr_gr_table_ptr == NULL) {
                 return -EINVAL;
+        }
 
         memcpy(&header, lpwr_gr_table_ptr,
                 sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header));
@@ -106,9 +109,10 @@ static int get_lpwr_gr_table(struct gk20a *g)
                                 NVGPU_PMU_GR_FEATURE_MASK_ALL;
 
                         if (!BIOS_GET_FIELD(entry.feautre_mask,
-                                NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG))
+                                NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG)) {
                                 pgr_data->entry[idx].feature_mask &=
                                         ~NVGPU_PMU_GR_FEATURE_MASK_RPPG;
+                        }
                 }
 
         }
@@ -128,14 +132,16 @@ static int get_lpwr_ms_table(struct gk20a *g)
 
         lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
                 g->bios.perf_token, LOWPOWER_MS_TABLE);
-        if (lpwr_ms_table_ptr == NULL)
+        if (lpwr_ms_table_ptr == NULL) {
                 return -EINVAL;
+        }
 
         memcpy(&header, lpwr_ms_table_ptr,
                 sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header));
 
-        if (header.entry_count >= LPWR_VBIOS_MS_ENTRY_COUNT_MAX)
+        if (header.entry_count >= LPWR_VBIOS_MS_ENTRY_COUNT_MAX) {
                 return -EINVAL;
+        }
 
         pms_data->default_entry_idx = (u8)header.default_entry_idx;
 
@@ -157,19 +163,22 @@ static int get_lpwr_ms_table(struct gk20a *g)
                                 NVGPU_PMU_MS_FEATURE_MASK_ALL;
 
                         if (!BIOS_GET_FIELD(entry.feautre_mask,
-                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING))
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING)) {
                                 pms_data->entry[idx].feature_mask &=
                                         ~NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING;
+                        }
 
                         if (!BIOS_GET_FIELD(entry.feautre_mask,
-                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR))
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR)) {
                                 pms_data->entry[idx].feature_mask &=
                                         ~NVGPU_PMU_MS_FEATURE_MASK_SW_ASR;
+                        }
 
                         if (!BIOS_GET_FIELD(entry.feautre_mask,
-                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG))
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG)) {
                                 pms_data->entry[idx].feature_mask &=
                                         ~NVGPU_PMU_MS_FEATURE_MASK_RPPG;
+                        }
                 }
 
                 pms_data->entry[idx].dynamic_current_logic =
@@ -189,12 +198,14 @@ u32 nvgpu_lpwr_pg_setup(struct gk20a *g)
         nvgpu_log_fn(g, " ");
 
         err = get_lpwr_gr_table(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = get_lpwr_ms_table(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = get_lpwr_idx_table(g);
 
@@ -232,13 +243,15 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
 
         pstate_info = pstate_get_clk_set_info(g, pstate,
                         clkwhich_mclk);
-        if (!pstate_info)
+        if (!pstate_info) {
                 return -EINVAL;
+        }
 
         if (pstate_info->max_mhz >
-                        MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ)
+                        MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ) {
                 payload |=
                         NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED;
+        }
 
         if (payload != g->perf_pmu.lpwr.mclk_change_cache) {
                 g->perf_pmu.lpwr.mclk_change_cache = payload;
@@ -311,14 +324,16 @@ u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num)
 
         nvgpu_log_fn(g, " ");
 
-        if (!pstate)
+        if (!pstate) {
                 return 0;
+        }
 
         ms_idx = pidx_data->entry[pstate->lpwr_entry_idx].ms_idx;
-        if (pms_data->entry[ms_idx].ms_enabled)
+        if (pms_data->entry[ms_idx].ms_enabled) {
                 return 1;
-        else
+        } else {
                 return 0;
+        }
 }
 
 u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
@@ -332,14 +347,16 @@ u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
 
         nvgpu_log_fn(g, " ");
 
-        if (!pstate)
+        if (!pstate) {
                 return 0;
+        }
 
         idx = pidx_data->entry[pstate->lpwr_entry_idx].gr_idx;
-        if (pgr_data->entry[idx].gr_enabled)
+        if (pgr_data->entry[idx].gr_enabled) {
                 return 1;
-        else
+        } else {
                 return 0;
+        }
 }
 
 
@@ -353,8 +370,9 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
 
         nvgpu_log_fn(g, " ");
 
-        if (pstate_lock)
+        if (pstate_lock) {
                 nvgpu_clk_arb_pstate_change_lock(g, true);
+        }
         nvgpu_mutex_acquire(&pmu->pg_mutex);
 
         present_pstate = nvgpu_clk_arb_get_current_pstate(g);
@@ -362,20 +380,23 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
         is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
                         present_pstate);
         if (is_mscg_supported && g->mscg_enabled) {
-                if (!pmu->mscg_stat)
+                if (!pmu->mscg_stat) {
                         pmu->mscg_stat = PMU_MSCG_ENABLED;
+                }
         }
 
         is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g,
                         present_pstate);
         if (is_rppg_supported) {
-                if (g->support_pmu && g->can_elpg)
+                if (g->support_pmu && g->can_elpg) {
                         status = nvgpu_pmu_enable_elpg(g);
+                }
         }
 
         nvgpu_mutex_release(&pmu->pg_mutex);
-        if (pstate_lock)
+        if (pstate_lock) {
                 nvgpu_clk_arb_pstate_change_lock(g, false);
+        }
 
         return status;
 }
@@ -390,8 +411,9 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
 
         nvgpu_log_fn(g, " ");
 
-        if (pstate_lock)
+        if (pstate_lock) {
                 nvgpu_clk_arb_pstate_change_lock(g, true);
+        }
         nvgpu_mutex_acquire(&pmu->pg_mutex);
 
         present_pstate = nvgpu_clk_arb_get_current_pstate(g);
@@ -401,22 +423,25 @@ int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
         if (is_rppg_supported) {
                 if (g->support_pmu && g->elpg_enabled) {
                         status = nvgpu_pmu_disable_elpg(g);
-                        if (status)
+                        if (status) {
                                 goto exit_unlock;
+                        }
                 }
         }
 
         is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
                         present_pstate);
         if (is_mscg_supported && g->mscg_enabled) {
-                if (pmu->mscg_stat)
+                if (pmu->mscg_stat) {
                         pmu->mscg_stat = PMU_MSCG_DISABLED;
+                }
         }
 
 exit_unlock:
         nvgpu_mutex_release(&pmu->pg_mutex);
-        if (pstate_lock)
+        if (pstate_lock) {
                 nvgpu_clk_arb_pstate_change_lock(g, false);
+        }
 
         nvgpu_log_fn(g, "done");
         return status;
diff --git a/drivers/gpu/nvgpu/perf/perf.c b/drivers/gpu/nvgpu/perf/perf.c
index 71bbcd40..f8b1daf0 100644
--- a/drivers/gpu/nvgpu/perf/perf.c
+++ b/drivers/gpu/nvgpu/perf/perf.c
@@ -46,8 +46,9 @@ static void perfrpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                 return;
         }
 
-        if (phandlerparams->prpccall->b_supported)
+        if (phandlerparams->prpccall->b_supported) {
                 phandlerparams->success = 1;
+        }
 }
 
 static int pmu_handle_perf_event(struct gk20a *g, void *pmu_msg)
diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c
index fdeee9a7..8b308f37 100644
--- a/drivers/gpu/nvgpu/perf/vfe_equ.c
+++ b/drivers/gpu/nvgpu/perf/vfe_equ.c
@@ -62,8 +62,9 @@ static int _vfe_equs_pmudata_instget(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         /* check whether pmuboardobjgrp has a valid boardobj in index */
-        if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS)
+        if (idx >= CTRL_BOARDOBJGRP_E255_MAX_OBJECTS) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &pgrp_set->objects[idx].data.board_obj;
@@ -105,8 +106,9 @@ int vfe_equ_sw_setup(struct gk20a *g)
         pboardobjgrp->pmudatainstget  = _vfe_equs_pmudata_instget;
 
         status = devinit_get_vfe_equ_table(g, pvfeequobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
 done:
         nvgpu_log_info(g, " done status %x", status);
@@ -122,8 +124,9 @@ int vfe_equ_pmu_setup(struct gk20a *g)
 
         pboardobjgrp = &g->perf_pmu.vfe_equobjs.super.super;
 
-        if (!pboardobjgrp->bconstructed)
+        if (!pboardobjgrp->bconstructed) {
                 return -EINVAL;
+        }
 
         status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
 
@@ -171,12 +174,12 @@ static int devinit_get_vfe_equ_table(struct gk20a *g,
         }
 
         if (vfeequs_tbl_header.vfe_equ_entry_size ==
-                        VBIOS_VFE_3X_EQU_ENTRY_SIZE_17)
+                        VBIOS_VFE_3X_EQU_ENTRY_SIZE_17) {
                 szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_17;
-        else if (vfeequs_tbl_header.vfe_equ_entry_size ==
-                        VBIOS_VFE_3X_EQU_ENTRY_SIZE_18)
+        } else if (vfeequs_tbl_header.vfe_equ_entry_size ==
+                        VBIOS_VFE_3X_EQU_ENTRY_SIZE_18) {
                 szfmt = VBIOS_VFE_3X_EQU_ENTRY_SIZE_18;
-        else {
+        } else {
                 status = -EINVAL;
                 goto done;
         }
@@ -340,8 +343,9 @@ static int _vfe_equ_pmudatainit_super(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_equ = (struct vfe_equ *)board_obj_ptr;
 
@@ -367,8 +371,9 @@ static int vfe_equ_construct_super(struct gk20a *g,
 
         status = boardobj_construct_super(g, ppboardobj,
                 size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfeequ = (struct vfe_equ *)*ppboardobj;
 
@@ -395,8 +400,9 @@ static int _vfe_equ_pmudatainit_compare(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_equ_compare = (struct vfe_equ_compare *)board_obj_ptr;
 
@@ -421,13 +427,15 @@ static int vfe_equ_construct_compare(struct gk20a *g,
                         (struct vfe_equ_compare *)pargs;
         int status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_COMPARE) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_COMPARE);
         status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfeequ = (struct vfe_equ_compare *)*ppboardobj;
 
@@ -454,8 +462,9 @@ static int _vfe_equ_pmudatainit_minmax(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_equ_minmax = (struct vfe_equ_minmax *)board_obj_ptr;
 
@@ -479,13 +488,15 @@ static int vfe_equ_construct_minmax(struct gk20a *g,
                         (struct vfe_equ_minmax *)pargs;
         int status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_MINMAX) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_MINMAX);
         status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfeequ = (struct vfe_equ_minmax *)*ppboardobj;
 
@@ -510,8 +521,9 @@ static int _vfe_equ_pmudatainit_quadratic(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_equ_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_equ_quadratic = (struct vfe_equ_quadratic *)board_obj_ptr;
 
@@ -535,13 +547,15 @@ static int vfe_equ_construct_quadratic(struct gk20a *g,
         int status = 0;
         u32 i;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_EQU_TYPE_QUADRATIC) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_EQU_TYPE_QUADRATIC);
         status = vfe_equ_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfeequ = (struct vfe_equ_quadratic *)*ppboardobj;
 
@@ -583,8 +597,9 @@ static struct vfe_equ *construct_vfe_equ(struct gk20a *g, void *pargs)
 
         }
 
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         nvgpu_log_info(g, " Done");
 
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c
index 5f6e9de7..9be069b0 100644
--- a/drivers/gpu/nvgpu/perf/vfe_var.c
+++ b/drivers/gpu/nvgpu/perf/vfe_var.c
@@ -72,8 +72,9 @@ static int _vfe_vars_pmudata_instget(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
-        if (idx >= CTRL_BOARDOBJGRP_E32_MAX_OBJECTS)
+        if (idx >= CTRL_BOARDOBJGRP_E32_MAX_OBJECTS) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &pgrp_set->objects[idx].data.board_obj;
@@ -90,8 +91,9 @@ static int _vfe_vars_pmustatus_instget(struct gk20a *g, void *pboardobjgrppmu,
                 pboardobjgrppmu;
 
         if (((u32)BIT(idx) &
-                pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
+                pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
                         &pgrp_get_status->objects[idx].data.board_obj;
@@ -134,8 +136,9 @@ int vfe_var_sw_setup(struct gk20a *g)
         pboardobjgrp->pmustatusinstget  = _vfe_vars_pmustatus_instget;
 
         status = devinit_get_vfe_var_table(g, pvfevarobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
                                 &g->perf_pmu.vfe_varobjs.super.super,
@@ -161,8 +164,9 @@ int vfe_var_pmu_setup(struct gk20a *g)
 
         pboardobjgrp = &g->perf_pmu.vfe_varobjs.super.super;
 
-        if (!pboardobjgrp->bconstructed)
+        if (!pboardobjgrp->bconstructed) {
                 return -EINVAL;
+        }
 
         status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
 
@@ -304,8 +308,9 @@ static int _vfe_var_pmudatainit_super(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var = (struct vfe_var *)board_obj_ptr;
         pset = (struct nv_pmu_vfe_var *) ppmudata;
@@ -332,8 +337,9 @@ static int vfe_var_construct_super(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = boardobj_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var *)*ppboardobj;
 
@@ -373,8 +379,9 @@ static int vfe_var_construct_derived(struct gk20a *g,
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED);
         status = vfe_var_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_derived *)*ppboardobj;
 
@@ -395,8 +402,9 @@ static int _vfe_var_pmudatainit_derived_product(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var_derived_product =
                 (struct vfe_var_derived_product *)board_obj_ptr;
@@ -418,13 +426,15 @@ static int vfe_var_construct_derived_product(struct gk20a *g,
                         (struct vfe_var_derived_product *)pargs;
         int status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_PRODUCT);
         status = vfe_var_construct_derived(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_derived_product *)*ppboardobj;
 
@@ -449,8 +459,9 @@ static int _vfe_var_pmudatainit_derived_sum(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_var_pmudatainit_derived(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var_derived_sum = (struct vfe_var_derived_sum *)board_obj_ptr;
         pset = (struct nv_pmu_vfe_var_derived_sum *)ppmudata;
@@ -471,13 +482,15 @@ static int vfe_var_construct_derived_sum(struct gk20a *g,
                         (struct vfe_var_derived_sum *)pargs;
         int status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_DERIVED_SUM);
         status = vfe_var_construct_derived(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_derived_sum *)*ppboardobj;
 
@@ -501,8 +514,9 @@ static int _vfe_var_pmudatainit_single(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_var_pmudatainit_super(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var_single = (struct vfe_var_single *)board_obj_ptr;
         pset = (struct nv_pmu_vfe_var_single *)
@@ -537,13 +551,15 @@ static u32 vfe_var_construct_single_frequency(struct gk20a *g,
 
         nvgpu_log_info(g, " ");
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_FREQUENCY);
         status = vfe_var_construct_single(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single_frequency *)*ppboardobj;
 
@@ -581,8 +597,9 @@ static int _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var_single_sensed_fuse =
                 (struct vfe_var_single_sensed_fuse *)board_obj_ptr;
@@ -618,8 +635,9 @@ static u32 vfe_var_construct_single_sensed(struct gk20a *g,
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED);
         status = vfe_var_construct_single(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single_sensed *)*ppboardobj;
 
@@ -643,13 +661,15 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g,
 
         nvgpu_log_info(g, " ");
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_FUSE);
         status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single_sensed_fuse *)*ppboardobj;
 
@@ -690,8 +710,9 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g,
                 goto exit;
         }
 exit:
-        if (status)
+        if (status) {
                 (*ppboardobj)->destruct(*ppboardobj);
+        }
 
         return status;
 }
@@ -707,8 +728,9 @@ static int _vfe_var_pmudatainit_single_sensed_temp(struct gk20a *g,
         nvgpu_log_info(g, " ");
 
         status = _vfe_var_pmudatainit_single_sensed(g, board_obj_ptr, ppmudata);
-        if (status != 0)
+        if (status != 0) {
                 return status;
+        }
 
         pvfe_var_single_sensed_temp =
                 (struct vfe_var_single_sensed_temp *)board_obj_ptr;
@@ -736,13 +758,15 @@ static u32 vfe_var_construct_single_sensed_temp(struct gk20a *g,
                         (struct vfe_var_single_sensed_temp *)pargs;
         u32 status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_SENSED_TEMP);
         status = vfe_var_construct_single_sensed(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single_sensed_temp *)*ppboardobj;
 
@@ -784,13 +808,15 @@ static int vfe_var_construct_single_voltage(struct gk20a *g,
         struct vfe_var_single_voltage *pvfevar;
         int status = 0;
 
-        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE)
+        if (BOARDOBJ_GET_TYPE(pargs) != CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE) {
                 return -EINVAL;
+        }
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE_VOLTAGE);
         status = vfe_var_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single_voltage *)*ppboardobj;
 
@@ -847,8 +873,9 @@ static struct vfe_var *construct_vfe_var(struct gk20a *g, void *pargs)
                 return NULL;
         }
 
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         nvgpu_log_info(g, "done");
 
@@ -896,12 +923,12 @@ static int devinit_get_vfe_var_table(struct gk20a *g,
         }
 
         if (vfevars_tbl_header.vfe_var_entry_size ==
-                        VBIOS_VFE_3X_VAR_ENTRY_SIZE_19)
+                        VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) {
                 szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_19;
-        else if (vfevars_tbl_header.vfe_var_entry_size ==
-                        VBIOS_VFE_3X_VAR_ENTRY_SIZE_11)
+        } else if (vfevars_tbl_header.vfe_var_entry_size ==
+                        VBIOS_VFE_3X_VAR_ENTRY_SIZE_11) {
                 szfmt = VBIOS_VFE_3X_VAR_ENTRY_SIZE_11;
-        else {
+        } else {
                 status = -EINVAL;
                 goto done;
         }
@@ -1047,8 +1074,9 @@ static int vfe_var_construct_single(struct gk20a *g,
 
         ptmpobj->type_mask |= BIT(CTRL_PERF_VFE_VAR_TYPE_SINGLE);
         status = vfe_var_construct_super(g, ppboardobj, size, pargs);
-        if (status)
+        if (status) {
                 return -EINVAL;
+        }
 
         pvfevar = (struct vfe_var_single *)*ppboardobj;
 
diff --git a/drivers/gpu/nvgpu/pmgr/pmgr.c b/drivers/gpu/nvgpu/pmgr/pmgr.c
index 6be0f82f..227a9893 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgr.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgr.c
@@ -30,9 +30,10 @@ int pmgr_pwr_devices_get_power(struct gk20a *g, u32 *val)
         int status;
 
         status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pwr_devices_get_current_power failed %x",
                         status);
+        }
 
         *val = payload.devices[0].powerm_w;
 
@@ -45,9 +46,10 @@ int pmgr_pwr_devices_get_current(struct gk20a *g, u32 *val)
         int status;
 
         status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pwr_devices_get_current failed %x",
                         status);
+        }
 
         *val = payload.devices[0].currentm_a;
 
@@ -60,9 +62,10 @@ int pmgr_pwr_devices_get_voltage(struct gk20a *g, u32 *val)
         int status;
 
         status = pmgr_pmu_pwr_devices_query_blocking(g, 1, &payload);
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pwr_devices_get_current_voltage failed %x",
                         status);
+        }
 
         *val = payload.devices[0].voltageu_v;
 
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 69c43a01..d0c0e763 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -168,9 +168,10 @@ static u32 pmgr_send_i2c_device_topology_to_pmu(struct gk20a *g)
                                 PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED,
                                 &i2c_desc_table);
 
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
                         status);
+        }
 
         return status;
 }
@@ -183,8 +184,9 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
 
         /* Set the BA-device-independent HW information */
         pwr_desc_table = nvgpu_kzalloc(g, sizeof(*pwr_desc_table));
-        if (!pwr_desc_table)
+        if (!pwr_desc_table) {
                 return -ENOMEM;
+        }
 
         ppwr_desc_header = &(pwr_desc_table->hdr.data);
         ppwr_desc_header->ba_info.b_initialized_and_used = false;
@@ -212,9 +214,10 @@ static int pmgr_send_pwr_device_topology_to_pmu(struct gk20a *g)
                                 (u16)sizeof(struct nv_pmu_pmgr_pwr_device_desc_table),
                                 pwr_desc_table);
 
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
                         status);
+        }
 
 exit:
         nvgpu_kfree(g, pwr_desc_table);
@@ -230,8 +233,9 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
         int status = 0;
 
         pwr_monitor_pack = nvgpu_kzalloc(g, sizeof(*pwr_monitor_pack));
-        if (!pwr_monitor_pack)
+        if (!pwr_monitor_pack) {
                 return -ENOMEM;
+        }
 
         /* Copy all the global settings from the RM copy */
         pwr_channel_hdr = &(pwr_monitor_pack->channels.hdr.data);
@@ -281,9 +285,10 @@ static int pmgr_send_pwr_mointer_to_pmu(struct gk20a *g)
                                 (u16)sizeof(struct nv_pmu_pmgr_pwr_monitor_pack),
                                 pwr_monitor_pack);
 
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
                         status);
+        }
 
 exit:
         nvgpu_kfree(g, pwr_monitor_pack);
@@ -365,9 +370,10 @@ static int pmgr_send_pwr_policy_to_pmu(struct gk20a *g)
                                 (u16)sizeof(struct nv_pmu_pmgr_pwr_policy_pack),
                                 ppwrpack);
 
-        if (status)
+        if (status) {
                 nvgpu_err(g, "pmgr_pmu_set_object failed %x",
                         status);
+        }
 
 exit:
         if (ppwrpack) {
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c
index 235629d6..90d39610 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c
@@ -40,8 +40,9 @@ static int _pwr_device_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0)
+                ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &ppmgrdevice->devices[idx].data.board_obj;
@@ -99,8 +100,9 @@ static struct boardobj *construct_pwr_device(struct gk20a *g,
 
         status = boardobj_construct_super(g, &board_obj_ptr,
                 pargs_size, pargs);
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         pwrdev = (struct pwr_device_ina3221*)board_obj_ptr;
 
@@ -250,8 +252,9 @@ static int devinit_get_pwr_device_table(struct gk20a *g,
                                 pwr_device_data.ina3221.curr_correct_m = (1 << 12);
                         }
                         pwr_device_size = sizeof(struct pwr_device_ina3221);
-                } else
+                } else {
                         continue;
+                }
 
                 pwr_device_data.boardobj.type = CTRL_PMGR_PWR_DEVICE_TYPE_INA3221;
                 pwr_device_data.pwrdev.power_rail = (u8)0;
@@ -306,8 +309,9 @@ int pmgr_device_sw_setup(struct gk20a *g)
         pboardobjgrp->pmudatainstget = _pwr_device_pmudata_instget;
 
         status = devinit_get_pwr_device_table(g, ppwrdeviceobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
 done:
         nvgpu_log_info(g, " done status %x", status);
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
index 53c7a1c4..9b2f91de 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
@@ -40,8 +40,9 @@ static int _pwr_channel_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0)
+                ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &ppmgrchannel->channels[idx].data.board_obj;
@@ -66,8 +67,9 @@ static int _pwr_channel_rels_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0)
+                ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &ppmgrchrels->ch_rels[idx].data.board_obj;
@@ -150,8 +152,9 @@ static struct boardobj *construct_pwr_topology(struct gk20a *g,
 
         status = boardobj_construct_super(g, &board_obj_ptr,
                 pargs_size, pargs);
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         pwrchannel = (struct pwr_channel_sensor*)board_obj_ptr;
 
@@ -253,8 +256,9 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
                                 NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX);
 
                         pwr_topology_size = sizeof(struct pwr_channel_sensor);
-                } else
+                } else {
                         continue;
+                }
 
                 /* Initialize data for the parent class */
                 pwr_topology_data.boardobj.type = CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR;
@@ -345,12 +349,14 @@ int pmgr_monitor_sw_setup(struct gk20a *g)
         ppwrmonitorobjs = &(g->pmgr_pmu.pmgr_monitorobjs);
 
         status = devinit_get_pwr_topology_table(g, ppwrmonitorobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         status = _pwr_channel_state_init(g);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         /* Initialise physicalChannelMask */
         g->pmgr_pmu.pmgr_monitorobjs.physical_channel_mask = 0;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
index 13a94e4f..d3fd941e 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -264,8 +264,9 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g,
 
         status = boardobj_construct_super(g, &board_obj_ptr,
                 pargs_size, pargs);
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         pwrpolicyhwthreshold = (struct pwr_policy_hw_threshold*)board_obj_ptr;
         pwrpolicy = (struct pwr_policy *)board_obj_ptr;
@@ -575,8 +576,9 @@ static int devinit_get_pwr_policy_table(struct gk20a *g,
                         packed_entry->flags0,
                         NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS);
 
-                if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD)
+                if (class_type != NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD) {
                         continue;
+                }
 
                 /* unpack power policy table entry */
                 devinit_unpack_pwr_policy_entry(&entry, packed_entry);
@@ -759,8 +761,9 @@ int pmgr_policy_sw_setup(struct gk20a *g)
         pboardobjgrp = &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super);
 
         status = devinit_get_pwr_policy_table(g, ppwrpolicyobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         g->pmgr_pmu.pmgr_policyobjs.b_enabled = true;
 
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 9b7d9b7e..616d6747 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -35,8 +35,9 @@ static int pstate_sw_setup(struct gk20a *g);
 
 void gk20a_deinit_pstate_support(struct gk20a *g)
 {
-        if (g->ops.clk.mclk_deinit)
+        if (g->ops.clk.mclk_deinit) {
                 g->ops.clk.mclk_deinit(g);
+        }
 
         nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex);
 }
@@ -49,69 +50,84 @@ int gk20a_init_pstate_support(struct gk20a *g)
         nvgpu_log_fn(g, " ");
 
         err = volt_rail_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = volt_dev_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = volt_policy_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_vin_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_fll_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = therm_domain_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = vfe_var_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = vfe_equ_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_domain_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_vf_point_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_prog_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = pstate_sw_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         if(g->ops.clk.support_pmgr_domain) {
                 err = pmgr_domain_sw_setup(g);
-                if (err)
+                if (err) {
                         return err;
+                }
         }
 
         if (g->ops.clk.support_clk_freq_controller) {
                 err = clk_freq_controller_sw_setup(g);
-                if (err)
+                if (err) {
                         return err;
+                }
         }
 
         if(g->ops.clk.support_lpwr_pg) {
                 err = nvgpu_lpwr_pg_setup(g);
-                if (err)
+                if (err) {
                         return err;
+                }
         }
 
         return err;
@@ -133,16 +149,19 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
         }
 
         err = volt_rail_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = volt_dev_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = volt_policy_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = g->ops.pmu_ver.volt.volt_send_load_cmd_to_pmu(g);
         if (err) {
@@ -153,52 +172,64 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g)
         }
 
         err = therm_domain_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = vfe_var_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = vfe_equ_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_domain_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_prog_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_vin_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_fll_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = clk_vf_point_pmu_setup(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         if (g->ops.clk.support_clk_freq_controller) {
                 err = clk_freq_controller_pmu_setup(g);
-                if (err)
+                if (err) {
                         return err;
+                }
         }
         err = clk_pmu_vin_load(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = g->ops.pmu_ver.clk.perf_pmu_vfe_load(g);
-        if (err)
+        if (err) {
                 return err;
+        }
 
-        if (g->ops.clk.support_pmgr_domain)
+        if (g->ops.clk.support_pmgr_domain) {
                 err = pmgr_domain_pmu_setup(g);
+        }
 
         return err;
 }
@@ -211,8 +242,9 @@ static int pstate_construct_super(struct gk20a *g, struct boardobj **ppboardobj,
         int err;
 
         err = boardobj_construct_super(g, ppboardobj, size, args);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         pstate = (struct pstate *)*ppboardobj;
 
@@ -239,9 +271,10 @@ static struct pstate *pstate_construct(struct gk20a *g, void *args)
 
         if ((tmp->super.type != CTRL_PERF_PSTATE_TYPE_3X) ||
             (pstate_construct_3x(g, (struct boardobj **)&pstate,
-                            sizeof(struct pstate), args)))
+                            sizeof(struct pstate), args))) {
                 nvgpu_err(g,
                         "error constructing pstate num=%u", tmp->num);
+        }
 
         return pstate;
 }
@@ -330,8 +363,9 @@ static int parse_pstate_table_5x(struct gk20a *g,
                 ((hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2) &&
                  (hdr->base_entry_size != VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3)) ||
                 (hdr->clock_entry_size != VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6) ||
-                (hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE))
+                (hdr->clock_entry_count > CLK_SET_INFO_MAX_SIZE)) {
                 return -EINVAL;
+        }
 
         p += hdr->header_size;
 
@@ -341,20 +375,24 @@ static int parse_pstate_table_5x(struct gk20a *g,
         for (i = 0; i < hdr->base_entry_count; i++, p += entry_size) {
                 entry = (struct vbios_pstate_entry_5x *)p;
 
-                if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY)
+                if (entry->pstate_level == VBIOS_PERFLEVEL_SKIP_ENTRY) {
                         continue;
+                }
 
                 err = parse_pstate_entry_5x(g, hdr, entry, &_pstate);
-                if (err)
+                if (err) {
                         goto done;
+                }
 
                 pstate = pstate_construct(g, &_pstate);
-                if (!pstate)
+                if (!pstate) {
                         goto done;
+                }
 
                 err = pstate_insert(g, pstate, i);
-                if (err)
+                if (err) {
                         goto done;
+                }
         }
 
 done:
@@ -371,8 +409,9 @@ static int pstate_sw_setup(struct gk20a *g)
         nvgpu_cond_init(&g->perf_pmu.pstatesobjs.pstate_notifier_wq);
 
         err = nvgpu_mutex_init(&g->perf_pmu.pstatesobjs.pstate_mutex);
-        if (err)
+        if (err) {
                 return err;
+        }
 
         err = boardobjgrpconstruct_e32(g, &g->perf_pmu.pstatesobjs.super);
         if (err) {
@@ -401,8 +440,9 @@ static int pstate_sw_setup(struct gk20a *g)
 
         err = parse_pstate_table_5x(g, hdr);
 done:
-        if (err)
+        if (err) {
                 nvgpu_mutex_destroy(&g->perf_pmu.pstatesobjs.pstate_mutex);
+        }
         return err;
 }
 
@@ -418,8 +458,9 @@ struct pstate *pstate_find(struct gk20a *g, u32 num)
                         struct pstate *, pstate, i) {
                 nvgpu_log_info(g, "pstate=%p num=%u (looking for num=%u)",
                                 pstate, pstate->num, num);
-                if (pstate->num == num)
+                if (pstate->num == num) {
                         return pstate;
+                }
         }
         return NULL;
 }
@@ -433,13 +474,15 @@ struct clk_set_info *pstate_get_clk_set_info(struct gk20a *g,
 
         nvgpu_log_info(g, "pstate = %p", pstate);
 
-        if (!pstate)
+        if (!pstate) {
                 return NULL;
+        }
 
         for (clkidx = 0; clkidx < pstate->clklist.num_info; clkidx++) {
                 info = &pstate->clklist.clksetinfo[clkidx];
-                if (info->clkwhich == clkwhich)
+                if (info->clkwhich == clkwhich) {
                         return info;
+                }
         }
         return NULL;
 }
diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c
index 7d196422..8130656c 100644
--- a/drivers/gpu/nvgpu/therm/thrmchannel.c
+++ b/drivers/gpu/nvgpu/therm/thrmchannel.c
@@ -73,8 +73,9 @@ static struct boardobj *construct_channel_device(struct gk20a *g,
 
         status = boardobj_construct_super(g, &board_obj_ptr,
                 pargs_size, pargs);
-        if (status)
+        if (status) {
                 return NULL;
+        }
 
         /* Set Super class interfaces */
         board_obj_ptr->pmudatainit = _therm_channel_pmudatainit_device;
@@ -108,8 +109,9 @@ static int _therm_channel_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                        pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
+                        pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &pgrp_set->objects[idx].data.board_obj;
@@ -233,8 +235,9 @@ int therm_channel_sw_setup(struct gk20a *g)
         pboardobjgrp->pmudatainstget = _therm_channel_pmudata_instget;
 
         status = devinit_get_therm_channel_table(g, pthermchannelobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_CHANNEL);
 
diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c
index ddd1f280..b0e65af7 100644
--- a/drivers/gpu/nvgpu/therm/thrmdev.c
+++ b/drivers/gpu/nvgpu/therm/thrmdev.c
@@ -43,8 +43,9 @@ static int _therm_device_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                        pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
+                        pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) {
                 return -EINVAL;
+        }
 
         *ppboardobjpmudata = (struct nv_pmu_boardobj *)
                 &pgrp_set->objects[idx].data;
@@ -208,8 +209,9 @@ static struct boardobj *therm_device_construct(struct gk20a *g,
                 board_obj_ptr = NULL;
                 nvgpu_err(g,
                         "could not allocate memory for therm_device");
-                if (board_obj_ptr != NULL)
+                if (board_obj_ptr != NULL) {
                         nvgpu_kfree(g, board_obj_ptr);
+                }
         }
 
 
@@ -347,8 +349,9 @@ int therm_device_sw_setup(struct gk20a *g)
         pboardobjgrp->pmudatainstget = _therm_device_pmudata_instget;
 
         status = devinit_get_therm_device_table(g, pthermdeviceobjs);
-        if (status)
+        if (status) {
                 goto done;
+        }
 
         BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, THERM, THERM_DEVICE);
 
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c
index 7814cf5e..e23d1d63 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.c
@@ -43,11 +43,12 @@ static void therm_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                 return;
         }
 
-        if (!phandlerparams->prpccall->b_supported)
+        if (!phandlerparams->prpccall->b_supported) {
                 nvgpu_err(g, "RPC msg %x failed",
                         msg->msg.pmgr.msg_type);
-        else
+        } else {
                 phandlerparams->success = 1;
+        }
 }
 
 int therm_send_pmgr_tables_to_pmu(struct gk20a *g)