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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 15:42:42 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-10 15:24:22 -0400
commitbc4a0bd0acd1d9b09f753d97383caa542cbb728a (patch)
tree92c577530106d95967d4d15ddc1f3fed5fb17bdb
parent612acdc86b520a6c7d9e68058bb7b0d22c0e7bc8 (diff)
gpu: nvgpu: lpwr: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ie8c1a62a1c42b9d10f0e89bf2959593638803c9f Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457351 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Alex Waterman <alexw@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c6
-rw-r--r--drivers/gpu/nvgpu/lpwr/rppg.c12
2 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index b722a900..9ff7c2a7 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -201,7 +201,7 @@ static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g,
201 gk20a_dbg_fn(""); 201 gk20a_dbg_fn("");
202 202
203 if (status != 0) { 203 if (status != 0) {
204 gk20a_err(dev_from_gk20a(g), "LWPR PARAM cmd aborted"); 204 nvgpu_err(g, "LWPR PARAM cmd aborted");
205 return; 205 return;
206 } 206 }
207 207
@@ -252,7 +252,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
252 &ack_status, 1); 252 &ack_status, 1);
253 if (ack_status == 0) { 253 if (ack_status == 0) {
254 status = -EINVAL; 254 status = -EINVAL;
255 gk20a_err(dev_from_gk20a(g), "MCLK-CHANGE ACK failed"); 255 nvgpu_err(g, "MCLK-CHANGE ACK failed");
256 } 256 }
257 } 257 }
258 258
@@ -285,7 +285,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
285 &ack_status, 1); 285 &ack_status, 1);
286 if (ack_status == 0) { 286 if (ack_status == 0) {
287 status = -EINVAL; 287 status = -EINVAL;
288 gk20a_err(dev_from_gk20a(g), "post-init ack failed"); 288 nvgpu_err(g, "post-init ack failed");
289 } 289 }
290 290
291 return status; 291 return status;
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
index e90fd7f9..59948f35 100644
--- a/drivers/gpu/nvgpu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -68,7 +68,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
68 prppg_cmd->stats_reset.ctrl_id; 68 prppg_cmd->stats_reset.ctrl_id;
69 break; 69 break;
70 default: 70 default:
71 gk20a_err(dev_from_gk20a(g), "Inivalid RPPG command %d", 71 nvgpu_err(g, "Inivalid RPPG command %d",
72 prppg_cmd->cmn.cmd_id); 72 prppg_cmd->cmn.cmd_id);
73 return -1; 73 return -1;
74 } 74 }
@@ -76,7 +76,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
76 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 76 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
77 pmu_handle_rppg_init_msg, &success, &seq, ~0); 77 pmu_handle_rppg_init_msg, &success, &seq, ~0);
78 if (status) { 78 if (status) {
79 gk20a_err(dev_from_gk20a(g), "Unable to submit parameter command %d", 79 nvgpu_err(g, "Unable to submit parameter command %d",
80 prppg_cmd->cmn.cmd_id); 80 prppg_cmd->cmn.cmd_id);
81 goto exit; 81 goto exit;
82 } 82 }
@@ -86,7 +86,7 @@ static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
86 &success, 1); 86 &success, 1);
87 if (success == 0) { 87 if (success == 0) {
88 status = -EINVAL; 88 status = -EINVAL;
89 gk20a_err(dev_from_gk20a(g), "Ack for the parameter command %x", 89 nvgpu_err(g, "Ack for the parameter command %x",
90 prppg_cmd->cmn.cmd_id); 90 prppg_cmd->cmn.cmd_id);
91 } 91 }
92 } 92 }
@@ -127,7 +127,7 @@ u32 init_rppg(struct gk20a *g)
127 127
128 status = rppg_init(g); 128 status = rppg_init(g);
129 if (status != 0) { 129 if (status != 0) {
130 gk20a_err(dev_from_gk20a(g), 130 nvgpu_err(g,
131 "Failed to initialize RPPG in PMU: 0x%08x", status); 131 "Failed to initialize RPPG in PMU: 0x%08x", status);
132 return status; 132 return status;
133 } 133 }
@@ -135,7 +135,7 @@ u32 init_rppg(struct gk20a *g)
135 135
136 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR); 136 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR);
137 if (status != 0) { 137 if (status != 0) {
138 gk20a_err(dev_from_gk20a(g), 138 nvgpu_err(g,
139 "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x", 139 "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x",
140 status); 140 status);
141 return status; 141 return status;
@@ -143,7 +143,7 @@ u32 init_rppg(struct gk20a *g)
143 143
144 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS); 144 status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS);
145 if (status != 0) { 145 if (status != 0) {
146 gk20a_err(dev_from_gk20a(g), 146 nvgpu_err(g,
147 "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x", 147 "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x",
148 status); 148 status);
149 return status; 149 return status;