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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-07-06 11:50:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-07-09 01:42:37 -0400
commitbbebc611bc10a824d5d51fc2ea9d0408e350d26a (patch)
treef2d8705fb8ec1fedc8e6af18d61bf469a16fbdc6
parent6d8d5eb17796bcd70d172f196adbca3bd1b964c4 (diff)
gpu: nvgpu: Do not enable replayable fault for context
Do not allow enabling replayable page faults in instace block. JIRA NVGPU-714 Change-Id: I9c48497e31798ab354a86d460a299e65774b388a Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1772863 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r--drivers/gpu/nvgpu/gp10b/fifo_gp10b.c27
1 files changed, 0 insertions, 27 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
index fd4ec34e..64bf4647 100644
--- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c
@@ -38,30 +38,6 @@
38#include <nvgpu/hw/gp10b/hw_ram_gp10b.h> 38#include <nvgpu/hw/gp10b/hw_ram_gp10b.h>
39#include <nvgpu/hw/gp10b/hw_top_gp10b.h> 39#include <nvgpu/hw/gp10b/hw_top_gp10b.h>
40 40
41static void gp10b_set_pdb_fault_replay_flags(struct gk20a *g,
42 struct nvgpu_mem *mem)
43{
44 u32 val;
45
46 nvgpu_log_fn(g, " ");
47
48 val = nvgpu_mem_rd32(g, mem,
49 ram_in_page_dir_base_fault_replay_tex_w());
50 val &= ~ram_in_page_dir_base_fault_replay_tex_m();
51 val |= ram_in_page_dir_base_fault_replay_tex_true_f();
52 nvgpu_mem_wr32(g, mem,
53 ram_in_page_dir_base_fault_replay_tex_w(), val);
54
55 val = nvgpu_mem_rd32(g, mem,
56 ram_in_page_dir_base_fault_replay_gcc_w());
57 val &= ~ram_in_page_dir_base_fault_replay_gcc_m();
58 val |= ram_in_page_dir_base_fault_replay_gcc_true_f();
59 nvgpu_mem_wr32(g, mem,
60 ram_in_page_dir_base_fault_replay_gcc_w(), val);
61
62 nvgpu_log_fn(g, "done");
63}
64
65int channel_gp10b_commit_userd(struct channel_gk20a *c) 41int channel_gp10b_commit_userd(struct channel_gk20a *c)
66{ 42{
67 u32 addr_lo; 43 u32 addr_lo;
@@ -141,9 +117,6 @@ int channel_gp10b_setup_ramfc(struct channel_gk20a *c,
141 pbdma_runlist_timeslice_timescale_3_f() | 117 pbdma_runlist_timeslice_timescale_3_f() |
142 pbdma_runlist_timeslice_enable_true_f()); 118 pbdma_runlist_timeslice_enable_true_f());
143 119
144 if (flags & NVGPU_GPFIFO_FLAGS_REPLAYABLE_FAULTS_ENABLE)
145 gp10b_set_pdb_fault_replay_flags(c->g, mem);
146
147 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid)); 120 nvgpu_mem_wr32(g, mem, ram_fc_chid_w(), ram_fc_chid_id_f(c->chid));
148 121
149 if (c->is_privileged_channel) { 122 if (c->is_privileged_channel) {