diff options
author | kalyani chidambaram <kalyanic@nvidia.com> | 2018-04-27 19:47:37 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-11 07:11:08 -0400 |
commit | a7288b58676f14a847592b6d6dcbe9080dfb9edb (patch) | |
tree | 3f09ed4fefe9ca7789473674ab348b98402331c4 | |
parent | e540bf87ae619f910572568914be8eb58192761b (diff) |
gpu: nvgpu: pmc access through pmc driver
The pmc access has to be through pmc driver. This prevents the direct access
to pmc registers and supports onlt tz access to it in t210 platforms.
Bug 1811649
Change-Id: I235768a07fa93ce4cced656aade160bbd853be62
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704315
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c | 21 |
1 files changed, 5 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c index 5301b13d..74309942 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a_tegra.c | |||
@@ -55,6 +55,7 @@ | |||
55 | #include "os_linux.h" | 55 | #include "os_linux.h" |
56 | 56 | ||
57 | #include "../../../arch/arm/mach-tegra/iomap.h" | 57 | #include "../../../arch/arm/mach-tegra/iomap.h" |
58 | #include <soc/tegra/pmc.h> | ||
58 | 59 | ||
59 | #define TEGRA_GK20A_BW_PER_FREQ 32 | 60 | #define TEGRA_GK20A_BW_PER_FREQ 32 |
60 | #define TEGRA_GM20B_BW_PER_FREQ 64 | 61 | #define TEGRA_GM20B_BW_PER_FREQ 64 |
@@ -84,16 +85,6 @@ struct gk20a_emc_params { | |||
84 | }; | 85 | }; |
85 | #endif | 86 | #endif |
86 | 87 | ||
87 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | ||
88 | static inline u32 __maybe_unused pmc_read(unsigned long reg) | ||
89 | { | ||
90 | return readl(pmc + reg); | ||
91 | } | ||
92 | |||
93 | static inline void __maybe_unused pmc_write(u32 val, unsigned long reg) | ||
94 | { | ||
95 | writel_relaxed(val, pmc + reg); | ||
96 | } | ||
97 | #define MHZ_TO_HZ(x) ((x) * 1000000) | 88 | #define MHZ_TO_HZ(x) ((x) * 1000000) |
98 | #define HZ_TO_MHZ(x) ((x) / 1000000) | 89 | #define HZ_TO_MHZ(x) ((x) / 1000000) |
99 | 90 | ||
@@ -326,8 +317,8 @@ static int gm20b_tegra_railgate(struct device *dev) | |||
326 | udelay(10); | 317 | udelay(10); |
327 | 318 | ||
328 | /* enable clamp */ | 319 | /* enable clamp */ |
329 | pmc_write(0x1, PMC_GPU_RG_CNTRL_0); | 320 | tegra_pmc_writel_relaxed(0x1, PMC_GPU_RG_CNTRL_0); |
330 | pmc_read(PMC_GPU_RG_CNTRL_0); | 321 | tegra_pmc_readl(PMC_GPU_RG_CNTRL_0); |
331 | 322 | ||
332 | udelay(10); | 323 | udelay(10); |
333 | 324 | ||
@@ -435,8 +426,8 @@ static int gm20b_tegra_unrailgate(struct device *dev) | |||
435 | 426 | ||
436 | udelay(10); | 427 | udelay(10); |
437 | 428 | ||
438 | pmc_write(0, PMC_GPU_RG_CNTRL_0); | 429 | tegra_pmc_writel_relaxed(0, PMC_GPU_RG_CNTRL_0); |
439 | pmc_read(PMC_GPU_RG_CNTRL_0); | 430 | tegra_pmc_readl(PMC_GPU_RG_CNTRL_0); |
440 | 431 | ||
441 | udelay(10); | 432 | udelay(10); |
442 | 433 | ||
@@ -833,8 +824,6 @@ static int gk20a_tegra_probe(struct device *dev) | |||
833 | return ret; | 824 | return ret; |
834 | } | 825 | } |
835 | 826 | ||
836 | pmc = ioremap(TEGRA_PMC_BASE, 4096); | ||
837 | |||
838 | return 0; | 827 | return 0; |
839 | } | 828 | } |
840 | 829 | ||